In this paper, a design space exploration of power delivery networks is performed for multi-chip 2.5-D and 3-D IC technologies. The focus of the paper is the effective placement of the voltage regulator modules (VRMs) for power supply noise (PSN) suppression. Multiple on-package VRM configurations have been analyzed and compared. Additionally, 3D IC chip-on-VRM and backside-of-the-package VRM configurations are studied. From the PSN perspective, the 3D IC chip-on-VRM case suppresses the PSN the most even with high current density hotspots. The paper also studies the impact of different parameters such as VRM-chip distance on the package, on-chip decoupling capacitor density, etc. on the PSN.
@article{arxiv.2008.03124,
title = {Design Space Exploration of Power Delivery For Advanced Packaging Technologies},
author = {Md Obaidul Hossen and Yang Zhang and Hesam Fathi Moghadam and Yue Zhang and Michael Dayringer and Muhannad S Bakir},
journal= {arXiv preprint arXiv:2008.03124},
year = {2020}
}