DeGS: A Scalable 3DGS Architecture via Decoupled Workload Parsing and Reorganization
Abstract
3D Gaussian Splatting (3DGS) has emerged as a leading technique for real-time novel view synthesis, yet existing 3DGS accelerators suffer from poor architectural scalability: increasing the number of PEs leads to marginal performance improvement during rendering. We identify that the root cause is the tightly coupled ``checking-while-blending'' dataflow, which exacerbates PE underutilization caused by spatial redundancy from irregular Gaussian coverage and temporal redundancy from asynchronous pixel-wise termination under parallel execution. To address this issue, we propose DeGS, a scalable architecture for efficient 3DGS inference. To systematically eliminate the redundancies inherent in rendering, DeGS exploits a decoupled dataflow, restructuring the coupled -checking, transmittance checking, and -blending of the standard rendering process into consecutive workload parsing, reorganization, and blending stages. This allows the fragmented, length-variable, and temporal-dependent workloads to be reorganized into compact, conflict-free, and dense workloads prior to blending, thereby significantly improving PE utilization during parallel blending. Implemented in 28 nm technology, DeGS achieves 2.36--7.25 throughput, 1.82--6.02 end-to-end speedup, and 1.59--4.42 energy efficiency over state-of-the-art 3DGS accelerators (GSCore, GBU, GCC) across diverse scenes and resolutions (720p to 8K). Moreover, scaling from 16 to 1024 PEs, DeGS maintains over 80\% PE utilization at high resolutions, significantly outperforming existing accelerators.
Keywords
Cite
@article{arxiv.2608.02099,
title = {DeGS: A Scalable 3DGS Architecture via Decoupled Workload Parsing and Reorganization},
author = {Minnan Pei and Gang Li and Zeyu Zhu and Siting Wang and Junwen Si and Zhuoran Song and Yu Feng and Fangxin Liu and Xiaoyao Liang and Jian Cheng},
journal= {arXiv preprint arXiv:2608.02099},
year = {2026}
}
Comments
Accepted to the 59th IEEE/ACM International Symposium on Microarchitecture (MICRO 2026)