The estimation of classical CMOS "constant-field" or "Dennard" scaling methods that define scaling factors for various dimensional and electrical parameters have become less accurate in the deep-submicron regime, which drives the need for better estimation approaches especially in the educational and research domains. We present DeepScaleTool, a tool for the accurate estimation of deep-submicron technology scaling by modeling and curve fitting published data by a leading commercial fabrication company for silicon fabrication technology generations from 130~nm to 7~nm for the key parameters of area, delay, and energy. Compared to 10~nm--7~nm scaling data published by a leading foundry, the DeepScaleTool achieves an error of 1.7% in area, 2.5% in delay, and 5% in power. This compares favorably with another leading academic estimation method that achieves an error of 24% in area, 9.1% in delay, and 24.9% in power.
@article{arxiv.2102.10195,
title = {DeepScaleTool : A Tool for the Accurate Estimation of Technology Scaling in the Deep-Submicron Era},
author = {Satyabrata Sarangi and Bevan Baas},
journal= {arXiv preprint arXiv:2102.10195},
year = {2021}
}
Comments
This paper has been accepted for the 2021 IEEE International Symposium on Circuits and Systems. \copyright 2021 IEEE. Copyright statements are posted on the first page. 5 Pages, 5 Figures