LLMs can generate SystemVerilog assertions (SVAs) from natural language specs, but single-pass outputs often lack functional coverage due to limited IC design understanding. We propose CoverAssert, an iterative framework that clusters semantic and AST-based structural features of assertions, maps them to specifications, and uses functional coverage feedback to guide LLMs in prioritizing uncovered points. Experiments on four open-source designs show that integrating CoverAssert with AssertLLM and Spec2Assertion improves average improvements of 9.57 % in branch coverage, 9.64 % in statement coverage, and 15.69 % in toggle coverage.
@article{arxiv.2604.06607,
title = {CoverAssert: Iterative LLM Assertion Generation Driven by Functional Coverage via Syntax-Semantic Representations},
author = {Yonghao Wang and Yang Yin and Hongqin Lyu and Jiaxin Zhou and Zhiteng Chao and Mingyu Shi and Wenchao Ding and Yunlin Du and Jing Ye and Tiancheng Wang and Huawei Li},
journal= {arXiv preprint arXiv:2604.06607},
year = {2026}
}