Topologically quantum error corrected logical gates are complex. Chains of errors can form in space and time and diagonally in spacetime. It is highly nontrivial to determine whether a given logical gate is free of low weight combinations of errors leading to failure. We report a new tool Nestcheck capable of analyzing an arbitrary topological computation and determining the minimum number of errors required to cause failure.
@article{arxiv.1210.4249,
title = {Checking the error correction strength of arbitrary surface code logical gates},
author = {Thomas J. Milburn and Austin G. Fowler},
journal= {arXiv preprint arXiv:1210.4249},
year = {2012}
}