We publish an extension of openQCD-1.6 with AVX-512 vector instructions using Intel intrinsics. Recent Intel processors support extended instruction sets with operations on 512-bit wide vectors, increasing both the capacity for floating point operations and register memory. Optimal use of the new capabilities requires reorganising data and floating point operations into these wider vector units. We report on the implementation and performance of the AVX-512 OpenQCD extension on clusters using Intel Knights Landing and Xeon Scalable (Skylake) CPUs. In complete HMC trajectories with physically relevant parameters we observe a performance increase of 5% to 10%.
Cite
@article{arxiv.1806.06043,
title = {AVX-512 extension to OpenQCD 1.6},
author = {Ed Bennett and Mark Dawson and Michele Mesiti and Jarno Rantaharju},
journal= {arXiv preprint arXiv:1806.06043},
year = {2018}
}
Comments
9 pages, 4 figures and 4 tables. Presented at The 36th Annual International Symposium on Lattice Field Theory (Lattice 2018), 22-28 July, 2018, Michigan State University, East Lansing, Michigan, USA