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AutoRAC: Automated Processing-in-Memory Accelerator Design for Recommender Systems

Hardware Architecture 2025-05-19 v1

Abstract

The performance bottleneck of deep-learning-based recommender systems resides in their backbone Deep Neural Networks. By integrating Processing-In-Memory~(PIM) architectures, researchers can reduce data movement and enhance energy efficiency, paving the way for next-generation recommender models. Nevertheless, achieving performance and efficiency gains is challenging due to the complexity of the PIM design space and the intricate mapping of operators. In this paper, we demonstrate that automated PIM design is feasible even within the most demanding recommender model design space, spanning over 105410^{54} possible architectures. We propose \methodname, which formulates the co-optimization of recommender models and PIM design as a combinatorial search over mixed-precision interaction operations, and parameterizes the search with a one-shot supernet encompassing all mixed-precision options. We comprehensively evaluate our approach on three Click-Through Rate benchmarks, showcasing the superiority of our automated design methodology over manual approaches. Our results indicate up to a 3.36×\times speedup, 1.68×\times area reduction, and 12.48×\times higher power efficiency compared to naively mapped searched designs and state-of-the-art handcrafted designs.

Keywords

Cite

@article{arxiv.2505.10748,
  title  = {AutoRAC: Automated Processing-in-Memory Accelerator Design for Recommender Systems},
  author = {Feng Cheng and Tunhou Zhang and Junyao Zhang and Jonathan Hao-Cheng Ku and Yitu Wang and Xiaoxuan Yang and Hai and Li and Yiran Chen},
  journal= {arXiv preprint arXiv:2505.10748},
  year   = {2025}
}

Comments

GLSVLSI 2025

R2 v1 2026-06-28T23:35:10.400Z