Asynchronous logic circuits and sheaf obstructions
Hardware Architecture
2010-08-17 v1
Abstract
This article exhibits a particular encoding of logic circuits into a sheaf formalism. The central result of this article is that there exists strictly more information available to a circuit designer in this setting than exists in static truth tables, but less than exists in event-level simulation. This information is related to the timing behavior of the logic circuits, and thereby provides a ``bridge'' between static logic analysis and detailed simulation.
Cite
@article{arxiv.1008.2729,
title = {Asynchronous logic circuits and sheaf obstructions},
author = {Michael Robinson},
journal= {arXiv preprint arXiv:1008.2729},
year = {2010}
}