English

Arithmetic Intensity Balancing Convolution for Hardware-aware Efficient Block Design

Machine Learning 2023-04-11 v1 Hardware Architecture Computer Vision and Pattern Recognition

Abstract

As deep learning advances, edge devices and lightweight neural networks are becoming more important. To reduce latency in the AI accelerator, it's essential to not only reduce FLOPs but also enhance hardware performance. We proposed an arithmetic intensity balancing convolution (ABConv) to address the issue of the overall intensity being limited by the small weight arithmetic intensity for convolution with a small spatial size. ABConv increased the maximum bound of overall arithmetic intensity and significantly reduced latency, without sacrificing accuracy. We tested the latency and hardware performance of ABConv on the Arm Ethos-U65 NPU in various configurations and used it to replace some of MobileNetV1 and ResNet50 in image classification for CIFAR100.

Keywords

Cite

@article{arxiv.2304.04016,
  title  = {Arithmetic Intensity Balancing Convolution for Hardware-aware Efficient Block Design},
  author = {Shinkook Choi and Junkyeong Choi},
  journal= {arXiv preprint arXiv:2304.04016},
  year   = {2023}
}

Comments

Accepted paper at the On-Device Intelligence Workshop in conjunction with MLSys Conference 2023

R2 v1 2026-06-28T09:55:29.237Z