Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators

Jan Moritz Joseph; Ananda Samajdar; Lingjun Zhu; Rainer Leupers; Sung-Kyu Lim; Thilo Pionteck; Tushar Krishna

Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators

Hardware Architecture 2021-02-19 v3

Authors: Jan Moritz Joseph , Ananda Samajdar , Lingjun Zhu , Rainer Leupers , Sung-Kyu Lim , Thilo Pionteck , Tushar Krishna

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Abstract

The everlasting demand for higher computing power for deep neural networks (DNNs) drives the development of parallel computing architectures. 3D integration, in which chips are integrated and connected vertically, can further increase performance because it introduces another level of spatial parallelism. Therefore, we analyze dataflows, performance, area, power and temperature of such 3D-DNN-accelerators. Monolithic and TSV-based stacked 3D-ICs are compared against 2D-ICs. We identify workload properties and architectural parameters for efficient 3D-ICs and achieve up to 9.14x speedup of 3D vs. 2D. We discuss area-performance trade-offs. We demonstrate applicability as the 3D-IC draws similar power as 2D-ICs and is not thermal limited.

Keywords

deep neural network acceleration computer architecture fpga accelerator

Cite

@article{arxiv.2012.12563,
  title  = {Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators},
  author = {Jan Moritz Joseph and Ananda Samajdar and Lingjun Zhu and Rainer Leupers and Sung-Kyu Lim and Thilo Pionteck and Tushar Krishna},
  journal= {arXiv preprint arXiv:2012.12563},
  year   = {2021}
}

Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators

Abstract

Keywords

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