Architectural considerations in the design of a third-generation superconducting quantum annealing processor
Quantum Physics
2021-08-06 v1
Abstract
Early generations of superconducting quantum annealing processors have provided a valuable platform for studying the performance of a scalable quantum computing technology. These studies have directly informed our approach to the design of the next-generation processor. Our design priorities for this generation include an increase in per-qubit connectivity, a problem Hamiltonian energy scale similar to previous generations, reduced Hamiltonian specification errors, and an increase in the processor scale that also leaves programming and readout times fixed or reduced. Here we discuss the specific innovations that resulted in a processor architecture that satisfies these design priorities.
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Cite
@article{arxiv.2108.02322,
title = {Architectural considerations in the design of a third-generation superconducting quantum annealing processor},
author = {Kelly Boothby and Colin Enderud and Trevor Lanting and Reza Molavi and Nicholas Tsai and Mark H. Volkmann and Fabio Altomare and Mohammad H. Amin and Michael Babcock and Andrew J. Berkley and Catia Baron Aznar and Martin Boschnak and Holly Christiani and Sara Ejtemaee and Bram Evert and Matthew Gullen and Markus Hager and Richard Harris and Emile Hoskinson and Jeremy P. Hilton and Kais Jooya and Ann Huang and Mark W. Johnson and Andrew D. King and Eric Ladizinsky and Ryan Li and Allison MacDonald and Teresa Medina Fernandez and Richard Neufeld and Mana Norouzpour and Travis Oh and Isil Ozfidan and Paul Paddon and Ilya Perminov and Gabriel Poulin-Lamarre and Thomas Prescott and Jack Raymond and Mauricio Reis and Chris Rich and Aidan Roy and Hossein Sadeghi Esfahani and Yuki Sato and Ben Sheldan and Anatoly Smirnov and Loren J. Swenson and Jed Whittaker and Jason Yao and Alexander Yarovoy and Paul I. Bunyk},
journal= {arXiv preprint arXiv:2108.02322},
year = {2021}
}