Networks-on-Chip (NoCs) used in commercial many-core processors typically incorporate priority arbitration. Moreover, they experience bursty traffic due to application workloads. However, most state-of-the-art NoC analytical performance analysis techniques assume fair arbitration and simple traffic models. To address these limitations, we propose an analytical modeling technique for priority-aware NoCs under bursty traffic. Experimental evaluations with synthetic and bursty traffic show that the proposed approach has less than 10% modeling error with respect to cycle-accurate NoC simulator.
@article{arxiv.2007.13951,
title = {Analytical Performance Modeling of NoCs under Priority Arbitration and Bursty Traffic},
author = {Sumit K. Mandal and Raid Ayoub and Michael Kishinevsky and Mohammad M. Islam and Umit Y. Ogras},
journal= {arXiv preprint arXiv:2007.13951},
year = {2020}
}
Comments
This paper will appear in a future issue of IEEE Embedded Systems Letters