We present an array of leaky integrate-and-fire (LIF) neuron circuits designed for the second-generation BrainScaleS mixed-signal 65-nm CMOS neuromorphic hardware. The neuronal array is embedded in the analog network core of a scaled-down prototype HICANN-DLS chip. Designed as continuous-time circuits, the neurons are highly tunable and reconfigurable elements with accelerated dynamics. Each neuron integrates input current from a multitude of incoming synapses and evokes a digital spike event output. The circuit offers a wide tuning range for synaptic and membrane time constants, as well as for refractory periods to cover a number of computational models. We elucidate our design methodology, underlying circuit design, calibration and measurement results from individual sub-circuits across multiple dies. The circuit dynamics match with the behavior of the LIF mathematical model. We further demonstrate a winner-take-all network on the prototype chip as a typical element of cortical processing.
@article{arxiv.1804.01906,
title = {An Accelerated LIF Neuronal Network Array for a Large Scale Mixed-Signal Neuromorphic Architecture},
author = {Syed Ahmed Aamir and Yannik Stradmann and Paul Müller and Christian Pehle and Andreas Hartel and Andreas Grübl and Johannes Schemmel and Karlheinz Meier},
journal= {arXiv preprint arXiv:1804.01906},
year = {2019}
}
Comments
14 pages, 9 Figures, accepted for publication in IEEE Transactions on Circuits and Systems I