English

Accelerating PoT Quantization on Edge Devices

Hardware Architecture 2024-10-23 v2 Machine Learning

Abstract

Non-uniform quantization, such as power-of-two (PoT) quantization, matches data distributions better than uniform quantization, which reduces the quantization error of Deep Neural Networks (DNNs). PoT quantization also allows bit-shift operations to replace multiplications, but there are limited studies on the efficiency of shift-based accelerators for PoT quantization. Furthermore, existing pipelines for accelerating PoT-quantized DNNs on edge devices are not open-source. In this paper, we first design shift-based processing elements (shift-PE) for different PoT quantization methods and evaluate their efficiency using synthetic benchmarks. Then we design a shift-based accelerator using our most efficient shift-PE and propose PoTAcc, an open-source pipeline for end-to-end acceleration of PoT-quantized DNNs on resource-constrained edge devices. Using PoTAcc, we evaluate the performance of our shift-based accelerator across three DNNs. On average, it achieves a 1.23x speedup and 1.24x energy reduction compared to a multiplier-based accelerator, and a 2.46x speedup and 1.83x energy reduction compared to CPU-only execution. Our code is available at https://github.com/gicLAB/PoTAcc

Keywords

Cite

@article{arxiv.2409.20403,
  title  = {Accelerating PoT Quantization on Edge Devices},
  author = {Rappy Saha and Jude Haris and José Cano},
  journal= {arXiv preprint arXiv:2409.20403},
  year   = {2024}
}

Comments

Accepted at 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2024

R2 v1 2026-06-28T19:02:29.333Z