We present the results of an R&D study of a specialized processor capable of precisely reconstructing events with hundreds of charged-particle tracks in pixel detectors at 40 MHz, thus suitable for processing LHC events at the full crossing frequency. For this purpose we design and test a massively parallel pattern-recognition algorithm, inspired by studies of the processing of visual images by the brain as it happens in nature. We find that high-quality tracking in large detectors is possible with sub-μs latencies when this algorithm is implemented in modern, high-speed, high-bandwidth FPGA devices. This opens a possibility of making track reconstruction happen transparently as part of the detector readout.
@article{arxiv.1406.7220,
title = {A Specialized Processor for Track Reconstruction at the LHC Crossing Rate},
author = {A. Abba and F. Bedeschi and M. Citterio and F. Caponio and A. Cusimano and A. Geraci and P. Marino and M. J. Morello and N. Neri and G. Punzi and A. Piucci and L. Ristori and F. Spinella and S. Stracka and D. Tonelli},
journal= {arXiv preprint arXiv:1406.7220},
year = {2014}
}
Comments
Presented by G.Punzi at the conference on "Instrumentation for Colliding Beam Physics" (INSTR14), 24 Feb to 1 Mar 2014, Novosibirsk, Russia. Submitted to JINST proceedings