Current implementations of quantum computers suffer from large numbers of control lines per qubit, becoming unmanageable with system scale up. Here, we discuss a sparse spin-qubit architecture featuring integrated control electronics significantly reducing the off-chip wire count. This quantum-classical hardware integration closes the feasibility gap towards a CMOS quantum computer.
@article{arxiv.1912.06461,
title = {A sparse spin qubit array with integrated control electronics},
author = {Jelmer M. Boter and Juan P. Dehollain and Jeroen P. G. van Dijk and Toivo Hensgens and Richard Versluis and James S. Clarke and Menno Veldhorst and Fabio Sebastiano and Lieven M. K. Vandersypen},
journal= {arXiv preprint arXiv:1912.06461},
year = {2021}
}
Comments
Paper accompanying an invited talk at the 2019 IEEE International Electron Devices Meeting (IEDM), December 7-11, 2019