Distributed, Parallel, and Cluster Computing · Computer Science
Dataflow Aware Mapping of Convolutional Neural Networks Onto Many-Core Platforms With Network-on-Chip Interconnect
Andreas Bytyn, René Ahlsdorf, Rainer Leupers, Gerd Ascheid
2020-06-23
Computer Vision and Pattern Recognition · Computer Science
Splitting Convolutional Neural Network Structures for Efficient Inference
Emad MalekHosseini, Mohsen Hajabdollahi, Nader Karimi, Shadrokh Samavi +1
2020-02-11
Machine Learning · Computer Science
Optimizing Memory Efficiency of Graph Neural Networks on Edge Computing Platforms
Ao Zhou, Jianlei Yang, Yeqi Gao, Tong Qiao +6
2021-04-13
Hardware Architecture · Computer Science
CMD: A Cache-assisted GPU Memory Deduplication Architecture
Wei Zhao, Dan Feng, Wei Tong, Xueliang Wei +1
2024-08-20
Hardware Architecture · Computer Science
OCCAM: Optimal Data Reuse for Convolutional Neural Networks
Ashish Gondimalla, Jianqiao Liu, T. N. Vijaykumar, Mithuna Thottethodi
2021-06-29
Distributed, Parallel, and Cluster Computing · Computer Science
ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators
Rachmad Vidya Wicaksana Putra, Muhammad Abdullah Hanif, Muhammad Shafique
2023-03-06
Machine Learning · Computer Science
CapStore: Energy-Efficient Design and Management of the On-Chip Memory for CapsuleNet Inference Accelerators
Alberto Marchisio, Muhammad Abdullah Hanif, Mohammad Taghi Teimoori, Muhammad Shafique
2019-04-15
Computer Vision and Pattern Recognition · Computer Science
Condensation-Net: Memory-Efficient Network Architecture with Cross-Channel Pooling Layers and Virtual Feature Maps
Tse-Wei Chen, Motoki Yoshinaga, Hongxing Gao, Wei Tao +4
2021-04-30
Distributed, Parallel, and Cluster Computing · Computer Science
Efficient Memory Management for GPU-based Deep Learning Systems
Junzhe Zhang, Sai Ho Yeung, Yao Shu, Bingsheng He +1
2019-03-18
Hardware Architecture · Computer Science
vMCU: Coordinated Memory Management and Kernel Optimization for DNN Inference on MCUs
Size Zheng, Renze Chen, Meng Li, Zihao Ye +2
2024-06-12
Hardware Architecture · Computer Science
The Processing Using Memory Paradigm:In-DRAM Bulk Copy, Initialization, Bitwise AND and OR
Vivek Seshadri, Onur Mutlu
2016-11-01
Machine Learning · Computer Science
Quantized Guided Pruning for Efficient Hardware Implementations of Convolutional Neural Networks
Ghouthi Boukli Hacene, Vincent Gripon, Matthieu Arzel, Nicolas Farrugia +1
2019-01-01
Hardware Architecture · Computer Science
3D-TrIM: A Memory-Efficient Spatial Computing Architecture for Convolution Workloads
Cristian Sestito, Ahmed J. Abdelmaksoud, Shady Agwa, Themis Prodromakis
2025-02-27
Hardware Architecture · Computer Science
Synapse Compression for Event-Based Convolutional-Neural-Network Accelerators
Lennart Bamberg, Arash Pourtaherian, Luc Waeijen, Anupam Chahar +1
2023-01-25
Machine Learning · Computer Science
Beyond Low-rank Decomposition: A Shortcut Approach for Efficient On-Device Learning
Le-Trung Nguyen, Ael Quelennec, Van-Tam Nguyen, Enzo Tartaglione
2025-07-25
Computer Vision and Pattern Recognition · Computer Science
RePr: Improved Training of Convolutional Filters
Aaditya Prakash, James Storer, Dinei Florencio, Cha Zhang
2019-02-26
Distributed, Parallel, and Cluster Computing · Computer Science
Distributed Out-of-Memory NMF on CPU/GPU Architectures
Ismael Boureima, Manish Bhattarai, Maksim Eren, Erik Skau +3
2023-09-14