Neural network hardware is considered an essential part of future edge devices. In this paper, we propose a binary-weight spiking neural network (BW-SNN) hardware architecture for low-power real-time object classification on edge platforms. This design stores a full neural network on-chip, and hence requires no off-chip bandwidth. The proposed systolic array maximizes data reuse for a typical convolutional layer. A 5-layer convolutional BW-SNN hardware is implemented in 90nm CMOS. Compared with state-of-the-art designs, the area cost and energy per classification are reduced by 7× and 23×, respectively, while also achieving a higher accuracy on the MNIST benchmark. This is also a pioneering SNN hardware architecture that supports advanced CNN architectures.
@article{arxiv.2003.06310,
title = {A Power-Efficient Binary-Weight Spiking Neural Network Architecture for Real-Time Object Classification},
author = {Pai-Yu Tan and Po-Yao Chuang and Yen-Ting Lin and Cheng-Wen Wu and Juin-Ming Lu},
journal= {arXiv preprint arXiv:2003.06310},
year = {2020}
}