A polynomial-time heuristic for Circuit-SAT
Computational Complexity
2007-05-23 v4 Data Structures and Algorithms
Abstract
In this paper is presented an heuristic that, in polynomial time and space in the input dimension, determines if a circuit describes a tautology or a contradiction. If the circuit is neither a tautology nor a contradiction, then the heuristic finds an assignment to the circuit inputs such that the circuit is satisfied.
Cite
@article{arxiv.cs/0511071,
title = {A polynomial-time heuristic for Circuit-SAT},
author = {Francesco Capasso},
journal= {arXiv preprint arXiv:cs/0511071},
year = {2007}
}
Comments
20 pages, 8 figures