English

A Near-Sensor Processing Accelerator for Approximate Local Binary Pattern Networks

Hardware Architecture 2022-10-14 v1

Abstract

In this work, a high-speed and energy-efficient comparator-based Near-Sensor Local Binary Pattern accelerator architecture (NS-LBP) is proposed to execute a novel local binary pattern deep neural network. First, inspired by recent LBP networks, we design an approximate, hardware-oriented, and multiply-accumulate (MAC)-free network named Ap-LBP for efficient feature extraction, further reducing the computation complexity. Then, we develop NS-LBP as a processing-in-SRAM unit and a parallel in-memory LBP algorithm to process images near the sensor in a cache, remarkably reducing the power consumption of data transmission to an off-chip processor. Our circuit-to-application co-simulation results on MNIST and SVHN data-sets demonstrate minor accuracy degradation compared to baseline CNN and LBP-network models, while NS-LBP achieves 1.25 GHz and energy-efficiency of 37.4 TOPS/W. NS-LBP reduces energy consumption by 2.2x and execution time by a factor of 4x compared to the best recent LBP-based networks.

Keywords

Cite

@article{arxiv.2210.06698,
  title  = {A Near-Sensor Processing Accelerator for Approximate Local Binary Pattern Networks},
  author = {Shaahin Angizi and Mehrdad Morsali and Sepehr Tabrizchi and Arman Roohi},
  journal= {arXiv preprint arXiv:2210.06698},
  year   = {2022}
}

Comments

10 pages, 11 figures, 4 tables

R2 v1 2026-06-28T03:30:35.510Z