Power ISA(TM) Version 3.1 has introduced a new family of matrix math instructions, collectively known as the Matrix-Multiply Assist (MMA) facility. The instructions in this facility implement numerical linear algebra operations on small matrices and are meant to accelerate computation-intensive kernels, such as matrix multiplication, convolution and discrete Fourier transform. These instructions have led to a power- and area-efficient implementation of a high throughput math engine in the future POWER10 processor. Performance per core is 4 times better, at constant frequency, than the previous generation POWER9 processor. We also advocate the use of compiler built-ins as the preferred way of leveraging these instructions, which we illustrate through case studies covering matrix multiplication and convolution.
@article{arxiv.2104.03142,
title = {A matrix math facility for Power ISA(TM) processors},
author = {José E. Moreira and Kit Barton and Steven Battle and Peter Bergner and Ramon Bertran and Puneeth Bhat and Pedro Caldeira and David Edelsohn and Gordon Fossum and Brad Frey and Nemanja Ivanovic and Chip Kerchner and Vincent Lim and Shakti Kapoor and Tulio Machado Filho and Silvia Melitta Mueller and Brett Olsson and Satish Sadasivam and Baptiste Saleil and Bill Schmidt and Rajalakshmi Srinivasaraghavan and Shricharan Srivatsan and Brian Thompto and Andreas Wagner and Nelson Wu},
journal= {arXiv preprint arXiv:2104.03142},
year = {2021}
}