A Hardware Implementation of Artificial Neural Network Using Field Programmable Gate Arrays
Instrumentation and Detectors
2009-11-13 v1
Abstract
An artificial neural network algorithm is implemented using a field programmable gate array hardware. One hidden layer is used in the feed-forward neural network structure in order to discriminate one class of patterns from the other class in real time. With five 8-bit input patterns, six hidden nodes, and one 8-bit output, the implemented hardware neural network makes decision on a set of input patterns in 11 clocks and the result is identical to what to expect from off-line computation. This implementation may be used in level 1 hardware triggers in high energy physics experiments
Cite
@article{arxiv.physics/0703041,
title = {A Hardware Implementation of Artificial Neural Network Using Field Programmable Gate Arrays},
author = {E. Won},
journal= {arXiv preprint arXiv:physics/0703041},
year = {2009}
}
Comments
13 pages, 4 figures, submitted to Nucl. Instr. Meth. A