The M{\o}lmer-S{\o}rensen gate, a cornerstone entangling operation in trapped-ion systems, represents a promising alternative to standard entangling gates in superconducting quantum architectures. However, its performance on superconducting hardware has remained unverified. In this work, we present a hardware-efficient implementation of the M{\o}lmer-S{\o}rensen gate and characterize its performance using quantum process tomography (QPT) on IBM Quantum's superconducting processors. Our implementation achieves a process fidelity of 92.47\% on the real quantum hardware, a performance competitive with the 93.02\% fidelity of the device's native controlled-NOT (CX) gate. Furthermore, for the ∣00⟩ input state, the gate prepares the target Bell state with 94.2% success probability, confirming its correct logical operation. These results demonstrate that non-native entangling gates can be optimized to perform on par with hardware-native operations. This work expands the effective gate set for algorithm design on fixed-architecture processors and provides a critical benchmark for cross-platform gate evaluation, underscoring the role of hardware-aware compilation in advancing noisy intermediate-scale quantum (NISQ) computing.