A Cost-Efficient Look-Up Table Based Binary Coded Decimal Adder Design
Hardware Architecture
2022-03-21 v1
Abstract
The BCD (Binary Coded Decimal) being the more accurate and human-readable representation with ease of conversion, is prevailing in the computing and electronic communication.In this paper, a tree-structured parallel BCD addition algorithm is proposed with the reduced time complexity. BCD adder is more effective with a LUT (Look-Up Table)-based design, due to FPGA (Field Programmable Gate Array) technology's enumerable benefits and applications. A size-minimal and depth-minimal LUT-based BCD adder circuit construction is the main contribution of this paper.
Keywords
Cite
@article{arxiv.2203.09665,
title = {A Cost-Efficient Look-Up Table Based Binary Coded Decimal Adder Design},
author = {Zarrin Tasnim Sworna and Mubin Ul Haque and Hafiz Md. Hasan Babu and Lafifa Jamal},
journal= {arXiv preprint arXiv:2203.09665},
year = {2022}
}
Comments
Sworna, Z.T., Haque, M.U., Babu, H.M.H. and Jamal, L., 2017. A cost-efficient look-up table based binary coded decimal adder design. In IEEE FTC (pp. 874-882)