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A Bit-Parallel Deterministic Stochastic Multiplier

Hardware Architecture 2023-02-17 v1 Emerging Technologies Machine Learning

Abstract

This paper presents a novel bit-parallel deterministic stochastic multiplier, which improves the area-energy-latency product by up to 10.6×\times104^4, while improving the computational error by 32.2\%, compared to three prior stochastic multipliers.

Cite

@article{arxiv.2302.08324,
  title  = {A Bit-Parallel Deterministic Stochastic Multiplier},
  author = {Sairam Sri Vatsavai and Ishan Thakkar},
  journal= {arXiv preprint arXiv:2302.08324},
  year   = {2023}
}

Comments

To Appear at IEEE ISQED 2023

R2 v1 2026-06-28T08:41:52.579Z