A 28 nm AI microcontroller with tightly coupled zero-standby power weight memory featuring standard logic compatible 4 Mb 4-bits/cell embedded flash technology
This study introduces a novel AI microcontroller optimized for cost-effective, battery-powered edge AI applications. Unlike traditional single bit/cell memory configurations, the proposed microcontroller integrates zero-standby power weight memory featuring standard logic compatible 4-bits/cell embedded flash technology tightly coupled to a Near-Memory Computing Unit. This architecture enables efficient and low-power AI acceleration. Advanced state mapping and an overstress-free word line (WL) driver circuit extend verify levels, ensuring robust 16 state cell margin. A ping-pong buffer reduces internal data movement while supporting simultaneous multi-bit processing. The fabricated microcontroller demonstrated high reliability, maintaining accuracy after 160 hours of unpowered baking at 125∘C.
@article{arxiv.2503.11660,
title = {A 28 nm AI microcontroller with tightly coupled zero-standby power weight memory featuring standard logic compatible 4 Mb 4-bits/cell embedded flash technology},
author = {Daewung Kim and Seong Hwan Jeon and Young Hee Jeon and Kyung-Bae Kwon and Jigon Kim and Yeounghun Choi and Hyunseung Cha and Kitae Kwon and Daesik Park and Jongseuk Lee and Sihwan Kim and Seung-Hwan Song},
journal= {arXiv preprint arXiv:2503.11660},
year = {2025}
}
Comments
6 pages, 8 figures, Accepted as a full paper by the 2025 EDGE AI FOUNDATION Austin