3SAT on an All-to-All-Connected CMOS Ising Solver Chip
Abstract
This work solves 3SAT, a classical NP-complete problem, on a CMOS-based Ising hardware chip with all-to-all connectivity. The paper addresses practical issues in going from algorithms to hardware. It considers several degrees of freedom in mapping the 3SAT problem to the chip - using multiple Ising formulations for 3SAT; exploring multiple strategies for decomposing large problems into subproblems that can be accommodated on the Ising chip; and executing a sequence of these subproblems on CMOS hardware to obtain the solution to the larger problem. These are evaluated within a software framework, and the results are used to identify the most promising formulations and decomposition techniques. These best approaches are then mapped to the all-to-all hardware, and the performance of 3SAT is evaluated on the chip. Experimental data shows that the deployed decomposition and mapping strategies impact SAT solution quality: without our methods, the CMOS hardware cannot achieve 3SAT solutions on SATLIB benchmarks.
Cite
@article{arxiv.2309.11017,
title = {3SAT on an All-to-All-Connected CMOS Ising Solver Chip},
author = {Hüsrev Cılasun and Ziqing Zeng and Ramprasath S and Abhimanyu Kumar and Hao Lo and William Cho and Chris H. Kim and Ulya R. Karpuzcu and Sachin S. Sapatnekar},
journal= {arXiv preprint arXiv:2309.11017},
year = {2026}
}