https://scifaro.com/en/abs/nature-inspired-interconnects-for-self-assembled-large-scale-network-on-chip-designs-0704.28522007-07-01 https://scifaro.com/zh/abs/nature-inspired-interconnects-for-self-assembled-large-scale-network-on-chip-designs-0704.28522007-07-01 https://scifaro.com/en/abs/a-methodology-for-efficient-space-time-adapter-design-space-exploration-a-case-study-of-an-ultra-wide-band-interleaver-0706.16922007-06-13 https://scifaro.com/zh/abs/a-methodology-for-efficient-space-time-adapter-design-space-exploration-a-case-study-of-an-ultra-wide-band-interleaver-0706.16922007-06-13 https://scifaro.com/en/abs/a-design-methodology-for-space-time-adapter-0706.27322007-06-20 https://scifaro.com/zh/abs/a-design-methodology-for-space-time-adapter-0706.27322007-06-20 https://scifaro.com/en/abs/m-ethodologie-de-mod-elisation-et-d-impl-ementation-d-adaptateurs-spatio-temporels-0706.28242007-06-20 https://scifaro.com/zh/abs/m-ethodologie-de-mod-elisation-et-d-impl-ementation-d-adaptateurs-spatio-temporels-0706.28242007-06-20 https://scifaro.com/en/abs/application-of-a-design-space-exploration-tool-to-enhance-interleaver-generation-0706.30092007-07-13 https://scifaro.com/zh/abs/application-of-a-design-space-exploration-tool-to-enhance-interleaver-generation-0706.30092007-07-13 https://scifaro.com/en/abs/logic-design-organization-of-ptvd-sham-a-parallel-time-varying-data-super-helical-access-memory-0707.11512015-03-13 https://scifaro.com/zh/abs/logic-design-organization-of-ptvd-sham-a-parallel-time-varying-data-super-helical-access-memory-0707.11512015-03-13 https://scifaro.com/en/abs/a-light-based-device-for-solving-the-hamiltonian-path-problem-0708.14962007-08-13 https://scifaro.com/zh/abs/a-light-based-device-for-solving-the-hamiltonian-path-problem-0708.14962007-08-13 https://scifaro.com/en/abs/solving-the-hamiltonian-path-problem-with-a-light-based-computer-0708.15122007-08-14 https://scifaro.com/zh/abs/solving-the-hamiltonian-path-problem-with-a-light-based-computer-0708.15122007-08-14 https://scifaro.com/en/abs/exact-cover-with-light-0708.19622009-02-07 https://scifaro.com/zh/abs/exact-cover-with-light-0708.19622009-02-07 https://scifaro.com/en/abs/solving-the-subset-sum-problem-with-a-light-based-device-0708.19642015-09-11 https://scifaro.com/zh/abs/solving-the-subset-sum-problem-with-a-light-based-device-0708.19642015-09-11 https://scifaro.com/en/abs/dpa-on-quasi-delay-insensitive-asynchronous-circuits-formalization-and-improvement-0710.34432007-10-19 https://scifaro.com/zh/abs/dpa-on-quasi-delay-insensitive-asynchronous-circuits-formalization-and-improvement-0710.34432007-10-19 https://scifaro.com/en/abs/janus-an-fpga-based-system-for-high-performance-scientific-computing-0710.35352017-05-02 https://scifaro.com/zh/abs/janus-an-fpga-based-system-for-high-performance-scientific-computing-0710.35352017-05-02 https://scifaro.com/en/abs/frequency-analysis-of-decoupling-capacitors-for-three-voltage-supplies-in-soc-0710.37892007-10-23 https://scifaro.com/zh/abs/frequency-analysis-of-decoupling-capacitors-for-three-voltage-supplies-in-soc-0710.37892007-10-23 https://scifaro.com/en/abs/caffeine-template-free-symbolic-model-generation-of-analog-circuits-via-canonical-form-functions-and-genetic-programming-0710.46302011-11-09 https://scifaro.com/en/abs/hardware-support-for-arbitrarily-complex-loop-structures-in-embedded-applications-0710.46322011-11-09 https://scifaro.com/en/abs/a-probabilistic-collocation-method-based-statistical-gate-delay-model-considering-process-variations-and-multiple-input-switching-0710.46342011-11-09 https://scifaro.com/zh/abs/a-probabilistic-collocation-method-based-statistical-gate-delay-model-considering-process-variations-and-multiple-input-switching-0710.46342011-11-09 https://scifaro.com/en/abs/why-systems-on-chip-needs-more-uml-like-a-hole-in-the-head-0710.46362011-11-09 https://scifaro.com/zh/abs/why-systems-on-chip-needs-more-uml-like-a-hole-in-the-head-0710.46362011-11-09 https://scifaro.com/en/abs/buffer-insertion-for-bridges-and-optimal-buffer-sizing-for-communication-sub-system-of-systems-on-chip-0710.46382011-11-09 https://scifaro.com/zh/abs/buffer-insertion-for-bridges-and-optimal-buffer-sizing-for-communication-sub-system-of-systems-on-chip-0710.46382011-11-09 https://scifaro.com/en/abs/modeling-the-non-linear-behavior-of-library-cells-for-an-accurate-static-noise-analysis-0710.46392011-11-09 https://scifaro.com/zh/abs/modeling-the-non-linear-behavior-of-library-cells-for-an-accurate-static-noise-analysis-0710.46392011-11-09 https://scifaro.com/en/abs/generic-pipelined-processor-modeling-and-high-performance-cycle-accurate-simulator-generation-0710.46432011-11-09 https://scifaro.com/zh/abs/generic-pipelined-processor-modeling-and-high-performance-cycle-accurate-simulator-generation-0710.46432011-11-09 https://scifaro.com/en/abs/cycle-accurate-binary-translation-for-simulation-acceleration-in-rapid-prototyping-of-socs-0710.46442011-11-09 https://scifaro.com/zh/abs/cycle-accurate-binary-translation-for-simulation-acceleration-in-rapid-prototyping-of-socs-0710.46442011-11-09 https://scifaro.com/en/abs/at-speed-logic-bist-for-ip-cores-0710.46452011-11-09 https://scifaro.com/zh/abs/at-speed-logic-bist-for-ip-cores-0710.46452011-11-09 https://scifaro.com/en/abs/fast-dynamic-memory-integration-in-co-simulation-frameworks-for-multiprocessor-system-on-chip-0710.46462011-11-09 https://scifaro.com/zh/abs/fast-dynamic-memory-integration-in-co-simulation-frameworks-for-multiprocessor-system-on-chip-0710.46462011-11-09 https://scifaro.com/en/abs/stochastic-power-grid-analysis-considering-process-variations-0710.46492011-11-09 https://scifaro.com/zh/abs/stochastic-power-grid-analysis-considering-process-variations-0710.46492011-11-09 https://scifaro.com/en/abs/locality-aware-process-scheduling-for-embedded-mpsocs-0710.46522011-11-09 https://scifaro.com/zh/abs/locality-aware-process-scheduling-for-embedded-mpsocs-0710.46522011-11-09 https://scifaro.com/en/abs/simultaneous-reduction-of-dynamic-and-static-power-in-scan-structures-0710.46532011-11-09 https://scifaro.com/zh/abs/simultaneous-reduction-of-dynamic-and-static-power-in-scan-structures-0710.46532011-11-09 https://scifaro.com/en/abs/modeling-interconnect-variability-using-efficient-parametric-model-order-reduction-0710.46542011-11-09 https://scifaro.com/zh/abs/modeling-interconnect-variability-using-efficient-parametric-model-order-reduction-0710.46542011-11-09 https://scifaro.com/en/abs/a-fast-diagnosis-scheme-for-distributed-small-embedded-srams-0710.46552011-11-09 https://scifaro.com/zh/abs/a-fast-diagnosis-scheme-for-distributed-small-embedded-srams-0710.46552011-11-09 https://scifaro.com/en/abs/a-memory-hierarchical-layer-assigning-and-prefetching-technique-to-overcome-the-memory-performance-energy-bottleneck-0710.46562011-11-09 https://scifaro.com/zh/abs/a-memory-hierarchical-layer-assigning-and-prefetching-technique-to-overcome-the-memory-performance-energy-bottleneck-0710.46562011-11-09 https://scifaro.com/en/abs/new-schemes-for-self-testing-ram-0710.46572011-11-09 https://scifaro.com/zh/abs/new-schemes-for-self-testing-ram-0710.46572011-11-09 https://scifaro.com/en/abs/compositional-memory-systems-for-multimedia-communicating-tasks-0710.46582011-11-09 https://scifaro.com/zh/abs/compositional-memory-systems-for-multimedia-communicating-tasks-0710.46582011-11-09 https://scifaro.com/en/abs/synchronization-processor-synthesis-for-latency-insensitive-systems-0710.46592011-11-09 https://scifaro.com/zh/abs/synchronization-processor-synthesis-for-latency-insensitive-systems-0710.46592011-11-09 https://scifaro.com/en/abs/thermal-aware-task-allocation-and-scheduling-for-embedded-systems-0710.46602011-11-09 https://scifaro.com/zh/abs/thermal-aware-task-allocation-and-scheduling-for-embedded-systems-0710.46602011-11-09 https://scifaro.com/en/abs/bright-field-aapsm-conflict-detection-and-correction-0710.46612011-11-09 https://scifaro.com/zh/abs/bright-field-aapsm-conflict-detection-and-correction-0710.46612011-11-09 https://scifaro.com/en/abs/statistical-modeling-of-pipeline-delay-and-design-of-pipeline-under-process-variation-to-enhance-yield-in-sub-100nm-technologies-0710.46632011-11-09 https://scifaro.com/zh/abs/statistical-modeling-of-pipeline-delay-and-design-of-pipeline-under-process-variation-to-enhance-yield-in-sub-100nm-technologies-0710.46632011-11-09 https://scifaro.com/en/abs/new-perspectives-and-opportunities-from-the-wild-west-of-microelectronic-biochips-0710.46652011-11-09 https://scifaro.com/zh/abs/new-perspectives-and-opportunities-from-the-wild-west-of-microelectronic-biochips-0710.46652011-11-09 https://scifaro.com/en/abs/integration-verification-and-layout-of-a-complex-multimedia-soc-0710.46672011-11-09 https://scifaro.com/zh/abs/integration-verification-and-layout-of-a-complex-multimedia-soc-0710.46672011-11-09 https://scifaro.com/en/abs/soc-testing-methodology-and-practice-0710.46692011-11-09 https://scifaro.com/en/abs/evolutionary-optimization-in-code-based-test-compression-0710.46702011-11-09 https://scifaro.com/en/abs/an-application-specific-design-methodology-for-stbus-crossbar-generation-0710.46712011-11-09 https://scifaro.com/en/abs/yield-enhancement-of-digital-microfluidics-based-biochips-using-space-redundancy-and-local-reconfiguration-0710.46722011-11-09 https://scifaro.com/en/abs/design-of-fault-tolerant-and-dynamically-reconfigurable-microfluidic-biochips-0710.46732011-11-09 https://scifaro.com/zh/abs/design-of-fault-tolerant-and-dynamically-reconfigurable-microfluidic-biochips-0710.46732011-11-09 https://scifaro.com/en/abs/cmos-based-biosensor-arrays-0710.46782011-11-09 https://scifaro.com/en/abs/dvs-for-on-chip-bus-designs-based-on-timing-error-correction-0710.46792011-11-09 https://scifaro.com/en/abs/a-quality-of-service-mechanism-for-interconnection-networks-in-system-on-chips-0710.46812011-11-09 https://scifaro.com/en/abs/reliability-centric-high-level-synthesis-0710.46842011-11-09 https://scifaro.com/zh/abs/reliability-centric-high-level-synthesis-0710.46842011-11-09 https://scifaro.com/en/abs/reliable-system-specification-for-self-checking-data-paths-0710.46852011-11-09 https://scifaro.com/zh/abs/reliable-system-specification-for-self-checking-data-paths-0710.46852011-11-09 https://scifaro.com/en/abs/test-planning-for-mixed-signal-socs-with-wrapped-analog-cores-0710.46862011-11-09 https://scifaro.com/zh/abs/test-planning-for-mixed-signal-socs-with-wrapped-analog-cores-0710.46862011-11-09 https://scifaro.com/en/abs/on-chip-test-infrastructure-design-for-optimal-multi-site-testing-of-system-chips-0710.46872011-11-09 https://scifaro.com/zh/abs/on-chip-test-infrastructure-design-for-optimal-multi-site-testing-of-system-chips-0710.46872011-11-09 https://scifaro.com/en/abs/on-the-optimal-design-of-triple-modular-redundancy-logic-for-sram-based-fpgas-0710.46882011-11-09 https://scifaro.com/zh/abs/on-the-optimal-design-of-triple-modular-redundancy-logic-for-sram-based-fpgas-0710.46882011-11-09 https://scifaro.com/en/abs/an-o-bn-2-time-algorithm-for-optimal-buffer-insertion-with-b-buffer-types-0710.46912011-11-09 https://scifaro.com/zh/abs/an-o-bn-2-time-algorithm-for-optimal-buffer-insertion-with-b-buffer-types-0710.46912011-11-09 https://scifaro.com/en/abs/cantilever-based-biosensors-in-cmos-technology-0710.46922011-11-09 https://scifaro.com/zh/abs/cantilever-based-biosensors-in-cmos-technology-0710.46922011-11-09 https://scifaro.com/en/abs/memory-testing-under-different-stress-conditions-an-industrial-evaluation-0710.46932011-11-09 https://scifaro.com/zh/abs/memory-testing-under-different-stress-conditions-an-industrial-evaluation-0710.46932011-11-09 https://scifaro.com/en/abs/statistical-timing-based-optimization-using-gate-sizing-0710.46972011-11-09 https://scifaro.com/zh/abs/statistical-timing-based-optimization-using-gate-sizing-0710.46972011-11-09 https://scifaro.com/en/abs/a-way-memoization-technique-for-reducing-power-consumption-of-caches-in-application-specific-integrated-processors-0710.47032011-11-09 https://scifaro.com/zh/abs/a-way-memoization-technique-for-reducing-power-consumption-of-caches-in-application-specific-integrated-processors-0710.47032011-11-09 https://scifaro.com/en/abs/resource-sharing-and-pipelining-in-coarse-grained-reconfigurable-architecture-for-domain-specific-optimization-0710.47042011-11-09 https://scifaro.com/zh/abs/resource-sharing-and-pipelining-in-coarse-grained-reconfigurable-architecture-for-domain-specific-optimization-0710.47042011-11-09 https://scifaro.com/en/abs/a-study-of-the-speedups-and-competitiveness-of-fpga-soft-processor-cores-using-dynamic-hardware-software-partitioning-0710.47052011-11-09 https://scifaro.com/zh/abs/a-study-of-the-speedups-and-competitiveness-of-fpga-soft-processor-cores-using-dynamic-hardware-software-partitioning-0710.47052011-11-09 https://scifaro.com/en/abs/an-infrastructure-to-functionally-test-designs-generated-by-compilers-targeting-fpgas-0710.47062011-11-09 https://scifaro.com/zh/abs/an-infrastructure-to-functionally-test-designs-generated-by-compilers-targeting-fpgas-0710.47062011-11-09 https://scifaro.com/en/abs/energy-and-performance-driven-noc-communication-architecture-synthesis-using-a-decomposition-approach-0710.47072011-11-09 https://scifaro.com/zh/abs/energy-and-performance-driven-noc-communication-architecture-synthesis-using-a-decomposition-approach-0710.47072011-11-09 https://scifaro.com/en/abs/analog-and-digital-circuit-design-in-65-nm-cmos-end-of-the-road-0710.47092011-11-09 https://scifaro.com/en/abs/fpga-architecture-for-multi-style-asynchronous-logic-0710.47112011-11-09 https://scifaro.com/en/abs/an-accurate-ser-estimation-method-based-on-propagation-probability-0710.47122011-11-09 https://scifaro.com/en/abs/improving-the-process-variation-tolerance-of-digital-circuits-using-gate-sizing-and-statistical-techniques-0710.47132011-11-09 https://scifaro.com/zh/abs/improving-the-process-variation-tolerance-of-digital-circuits-using-gate-sizing-and-statistical-techniques-0710.47132011-11-09 https://scifaro.com/en/abs/assertion-based-design-exploration-of-dvs-in-network-processor-architectures-0710.47142011-11-09 https://scifaro.com/zh/abs/assertion-based-design-exploration-of-dvs-in-network-processor-architectures-0710.47142011-11-09 https://scifaro.com/en/abs/circuit-level-modeling-for-concurrent-testing-of-operational-defects-due-to-gate-oxide-breakdown-0710.47152011-11-09 https://scifaro.com/zh/abs/circuit-level-modeling-for-concurrent-testing-of-operational-defects-due-to-gate-oxide-breakdown-0710.47152011-11-09 https://scifaro.com/en/abs/optimized-generation-of-data-path-from-c-codes-for-fpgas-0710.47162011-11-09 https://scifaro.com/zh/abs/optimized-generation-of-data-path-from-c-codes-for-fpgas-0710.47162011-11-09 https://scifaro.com/en/abs/multi-placement-structures-for-fast-and-optimized-placement-in-analog-circuit-synthesis-0710.47172011-11-09 https://scifaro.com/zh/abs/multi-placement-structures-for-fast-and-optimized-placement-in-analog-circuit-synthesis-0710.47172011-11-09 https://scifaro.com/en/abs/specification-test-compaction-for-analog-circuits-and-mems-0710.47192011-11-09 https://scifaro.com/zh/abs/specification-test-compaction-for-analog-circuits-and-mems-0710.47192011-11-09 https://scifaro.com/en/abs/soft-error-tolerance-analysis-and-optimization-of-nanometer-circuits-0710.47202011-11-09 https://scifaro.com/zh/abs/soft-error-tolerance-analysis-and-optimization-of-nanometer-circuits-0710.47202011-11-09 https://scifaro.com/en/abs/ieee-1149-4-compatible-abms-for-basic-rf-measurements-0710.47212011-11-09 https://scifaro.com/zh/abs/ieee-1149-4-compatible-abms-for-basic-rf-measurements-0710.47212011-11-09 https://scifaro.com/en/abs/designer-driven-topology-optimization-for-pipelined-analog-to-digital-converters-0710.47222011-11-09 https://scifaro.com/zh/abs/designer-driven-topology-optimization-for-pipelined-analog-to-digital-converters-0710.47222011-11-09 https://scifaro.com/en/abs/systematic-figure-of-merit-computation-for-the-design-of-pipeline-adc-0710.47242011-11-09 https://scifaro.com/zh/abs/systematic-figure-of-merit-computation-for-the-design-of-pipeline-adc-0710.47242011-11-09 https://scifaro.com/en/abs/top-down-design-of-a-low-power-multi-channel-2-5-gbit-s-channel-gated-oscillator-clock-recovery-circuit-0710.47272011-11-09 https://scifaro.com/zh/abs/top-down-design-of-a-low-power-multi-channel-2-5-gbit-s-channel-gated-oscillator-clock-recovery-circuit-0710.47272011-11-09 https://scifaro.com/en/abs/energy-aware-routing-for-e-textile-applications-0710.47282011-11-09 https://scifaro.com/en/abs/modeling-and-analysis-of-loading-effect-in-leakage-of-nano-scaled-bulk-cmos-logic-circuits-0710.47292011-11-09 https://scifaro.com/en/abs/leakage-aware-interconnect-for-on-chip-network-0710.47312011-11-09 https://scifaro.com/en/abs/smart-temperature-sensor-for-thermal-testing-of-cell-based-ics-0710.47332011-11-09 https://scifaro.com/zh/abs/smart-temperature-sensor-for-thermal-testing-of-cell-based-ics-0710.47332011-11-09 https://scifaro.com/en/abs/worst-case-and-average-case-analysis-of-n-detection-test-sets-0710.47352011-11-09 https://scifaro.com/zh/abs/worst-case-and-average-case-analysis-of-n-detection-test-sets-0710.47352011-11-09 https://scifaro.com/en/abs/a-new-embedded-measurement-structure-for-edram-capacitor-0710.47362011-11-09 https://scifaro.com/zh/abs/a-new-embedded-measurement-structure-for-edram-capacitor-0710.47362011-11-09 https://scifaro.com/en/abs/exploring-noc-mapping-strategies-an-energy-and-timing-aware-technique-0710.47382011-11-09 https://scifaro.com/zh/abs/exploring-noc-mapping-strategies-an-energy-and-timing-aware-technique-0710.47382011-11-09 https://scifaro.com/en/abs/hardware-accelerated-power-estimation-0710.47422011-11-09 https://scifaro.com/zh/abs/hardware-accelerated-power-estimation-0710.47422011-11-09 https://scifaro.com/en/abs/an-efficient-transparent-test-scheme-for-embedded-word-oriented-memories-0710.47472011-11-09 https://scifaro.com/en/abs/systematic-transaction-level-modeling-of-embedded-systems-with-systemc-0710.47482011-11-09 https://scifaro.com/zh/abs/systematic-transaction-level-modeling-of-embedded-systems-with-systemc-0710.47482011-11-09 https://scifaro.com/en/abs/influence-of-memory-hierarchies-on-predictability-for-time-constrained-embedded-software-0710.47512011-11-09 https://scifaro.com/zh/abs/influence-of-memory-hierarchies-on-predictability-for-time-constrained-embedded-software-0710.47512011-11-09 https://scifaro.com/en/abs/design-of-a-virtual-component-neutral-network-on-chip-transaction-layer-0710.47542011-11-09 https://scifaro.com/zh/abs/design-of-a-virtual-component-neutral-network-on-chip-transaction-layer-0710.47542011-11-09 https://scifaro.com/en/abs/techniques-for-fast-transient-fault-grading-based-on-autonomous-emulation-0710.47572011-11-09 https://scifaro.com/zh/abs/techniques-for-fast-transient-fault-grading-based-on-autonomous-emulation-0710.47572011-11-09 https://scifaro.com/en/abs/a-fast-concurrent-power-thermal-model-for-sub-100nm-digital-ics-0710.47592011-11-09 https://scifaro.com/en/abs/low-power-oriented-cmos-circuit-optimization-protocol-0710.47602011-11-09 https://scifaro.com/en/abs/low-cost-multi-gigahertz-test-systems-using-cmos-fpgas-and-pecl-0710.47612011-11-09 https://scifaro.com/en/abs/area-efficient-selective-multi-threshold-cmos-design-methodology-for-standby-leakage-power-reduction-0710.47622011-11-09 https://scifaro.com/en/abs/logic-design-for-on-chip-test-clock-generation-implementation-details-and-impact-on-delay-test-quality-0710.47632011-11-09 https://scifaro.com/zh/abs/logic-design-for-on-chip-test-clock-generation-implementation-details-and-impact-on-delay-test-quality-0710.47632011-11-09 https://scifaro.com/en/abs/hotspot-prevention-through-runtime-reconfiguration-in-network-on-chip-0710.47642011-11-09 https://scifaro.com/zh/abs/hotspot-prevention-through-runtime-reconfiguration-in-network-on-chip-0710.47642011-11-09 https://scifaro.com/en/abs/power-performance-trade-offs-in-nanometer-scale-multi-level-caches-considering-total-leakage-0710.47942011-11-09 https://scifaro.com/zh/abs/power-performance-trade-offs-in-nanometer-scale-multi-level-caches-considering-total-leakage-0710.47942011-11-09 https://scifaro.com/en/abs/test-time-reduction-reusing-multiple-processors-in-a-network-on-chip-based-architecture-0710.47952011-11-09 https://scifaro.com/zh/abs/test-time-reduction-reusing-multiple-processors-in-a-network-on-chip-based-architecture-0710.47952011-11-09 https://scifaro.com/en/abs/a-hybrid-prefetch-scheduling-heuristic-to-minimize-at-run-time-the-reconfiguration-overhead-of-dynamically-reconfigurable-hardware-0710.47962011-11-09 https://scifaro.com/zh/abs/a-hybrid-prefetch-scheduling-heuristic-to-minimize-at-run-time-the-reconfiguration-overhead-of-dynamically-reconfigurable-hardware-0710.47962011-11-09 https://scifaro.com/en/abs/behavioural-transformation-to-improve-circuit-performance-in-high-level-synthesis-0710.48012011-11-09 https://scifaro.com/zh/abs/behavioural-transformation-to-improve-circuit-performance-in-high-level-synthesis-0710.48012011-11-09 https://scifaro.com/en/abs/modeling-of-a-reconfigurable-ofdm-ip-block-family-for-an-rf-system-simulator-0710.48052011-11-09 https://scifaro.com/zh/abs/modeling-of-a-reconfigurable-ofdm-ip-block-family-for-an-rf-system-simulator-0710.48052011-11-09 https://scifaro.com/en/abs/a-vlsi-design-flow-for-secure-side-channel-attack-resistant-ics-0710.48062011-11-09 https://scifaro.com/zh/abs/a-vlsi-design-flow-for-secure-side-channel-attack-resistant-ics-0710.48062011-11-09 https://scifaro.com/en/abs/fast-and-accurate-transaction-level-modeling-of-an-extended-amba2-0-bus-architecture-0710.48082011-11-09 https://scifaro.com/zh/abs/fast-and-accurate-transaction-level-modeling-of-an-extended-amba2-0-bus-architecture-0710.48082011-11-09 https://scifaro.com/en/abs/c-based-hardware-design-for-wireless-applications-0710.48092011-11-09 https://scifaro.com/zh/abs/c-based-hardware-design-for-wireless-applications-0710.48092011-11-09 https://scifaro.com/en/abs/area-and-throughput-trade-offs-in-the-design-of-pipelined-discrete-wavelet-transform-architectures-0710.48122011-11-09 https://scifaro.com/zh/abs/area-and-throughput-trade-offs-in-the-design-of-pipelined-discrete-wavelet-transform-architectures-0710.48122011-11-09 https://scifaro.com/en/abs/queue-management-in-network-processors-0710.48132011-11-09 https://scifaro.com/zh/abs/queue-management-in-network-processors-0710.48132011-11-09 https://scifaro.com/en/abs/picoarray-technology-the-tool-s-story-0710.48142011-11-09 https://scifaro.com/zh/abs/picoarray-technology-the-tool-s-story-0710.48142011-11-09 https://scifaro.com/en/abs/isegen-generation-of-high-quality-instruction-set-extensions-by-iterative-improvement-0710.48202011-11-09 https://scifaro.com/zh/abs/isegen-generation-of-high-quality-instruction-set-extensions-by-iterative-improvement-0710.48202011-11-09 https://scifaro.com/en/abs/fpga-based-agile-algorithm-on-demand-co-processor-0710.48242011-11-09 https://scifaro.com/en/abs/meeting-the-embedded-design-needs-of-automotive-applications-0710.48252011-11-09 https://scifaro.com/en/abs/the-integration-of-on-line-monitoring-and-reconfiguration-functions-using-edaa-european-design-and-automation-association1149-4-into-a-safety-critical-automotive-electronic-control-unit-0710.48262011-11-09 https://scifaro.com/en/abs/debug-support-calibration-and-emulation-for-multiple-processor-and-powertrain-control-socs-0710.48272011-11-09 https://scifaro.com/en/abs/systemc-analysis-of-a-new-dynamic-power-management-architecture-0710.48322011-11-09 https://scifaro.com/zh/abs/systemc-analysis-of-a-new-dynamic-power-management-architecture-0710.48322011-11-09 https://scifaro.com/en/abs/exploiting-real-time-fpga-based-adaptive-systems-technology-for-real-time-sensor-fusion-in-next-generation-automotive-safety-systems-0710.48332011-11-09 https://scifaro.com/zh/abs/exploiting-real-time-fpga-based-adaptive-systems-technology-for-real-time-sensor-fusion-in-next-generation-automotive-safety-systems-0710.48332011-11-09 https://scifaro.com/en/abs/platform-based-design-for-automotive-sensor-conditioning-0710.48342011-11-09 https://scifaro.com/zh/abs/platform-based-design-for-automotive-sensor-conditioning-0710.48342011-11-09 https://scifaro.com/en/abs/a-6bit-1-2gsps-low-power-flash-adc-in-0-13-mu-m-digital-cmos-0710.48382011-11-09 https://scifaro.com/zh/abs/a-6bit-1-2gsps-low-power-flash-adc-in-0-13-mu-m-digital-cmos-0710.48382011-11-09 https://scifaro.com/en/abs/a-97mw-110ms-s-12b-pipeline-adc-implemented-in-0-18-mu-m-digital-cmos-0710.48392011-11-09 https://scifaro.com/zh/abs/a-97mw-110ms-s-12b-pipeline-adc-implemented-in-0-18-mu-m-digital-cmos-0710.48392011-11-09 https://scifaro.com/en/abs/testing-logic-cores-using-a-bist-p1500-compliant-approach-a-case-of-study-0710.48402011-11-09 https://scifaro.com/zh/abs/testing-logic-cores-using-a-bist-p1500-compliant-approach-a-case-of-study-0710.48402011-11-09 https://scifaro.com/en/abs/using-mobilize-power-management-ip-for-dynamic-static-power-reduction-in-soc-at-130-nm-0710.48422011-11-09 https://scifaro.com/zh/abs/using-mobilize-power-management-ip-for-dynamic-static-power-reduction-in-soc-at-130-nm-0710.48422011-11-09 https://scifaro.com/en/abs/multinoc-a-multiprocessing-system-enabled-by-a-network-on-chip-0710.48432011-11-09 https://scifaro.com/zh/abs/multinoc-a-multiprocessing-system-enabled-by-a-network-on-chip-0710.48432011-11-09 https://scifaro.com/en/abs/a-partitioning-methodology-for-accelerating-applications-in-hybrid-reconfigurable-platforms-0710.48442011-11-09 https://scifaro.com/zh/abs/a-partitioning-methodology-for-accelerating-applications-in-hybrid-reconfigurable-platforms-0710.48442011-11-09 https://scifaro.com/en/abs/evaluation-of-systemc-modelling-of-reconfigurable-embedded-systems-0710.48452011-11-09 https://scifaro.com/zh/abs/evaluation-of-systemc-modelling-of-reconfigurable-embedded-systems-0710.48452011-11-09 https://scifaro.com/en/abs/hardware-support-for-qos-based-function-allocation-in-reconfigurable-systems-0710.48502011-11-09 https://scifaro.com/zh/abs/hardware-support-for-qos-based-function-allocation-in-reconfigurable-systems-0710.48502011-11-09 https://scifaro.com/en/abs/on-the-operating-unit-size-of-load-store-architectures-0711.08382010-05-12 https://scifaro.com/zh/abs/on-the-operating-unit-size-of-load-store-architectures-0711.08382010-05-12 https://scifaro.com/en/abs/decoding-the-golden-code-a-vlsi-design-0711.23832007-11-16 https://scifaro.com/en/abs/combined-integer-and-variable-precision-civp-floating-point-multiplication-architecture-for-fpgas-0711.26712007-11-19 https://scifaro.com/en/abs/partial-reversible-gates-prg-for-reversible-bcd-arithmetic-0711.26742007-11-19 https://scifaro.com/en/abs/transactional-wavecache-towards-speculative-and-out-of-order-dataflow-execution-of-memory-operations-0712.11672007-12-10 https://scifaro.com/en/abs/optimal-memoryless-encoding-for-low-power-off-chip-data-buses-0712.26402007-12-18 https://scifaro.com/en/abs/policies-of-system-level-pipeline-modeling-0801.22012008-01-16 https://scifaro.com/en/abs/efficient-implementation-of-gals-systems-over-commercial-synchronous-fpgas-a-new-approach-0802.34412008-02-26 https://scifaro.com/en/abs/assessing-random-dynamical-network-architectures-for-nanoelectronics-0805.26842016-11-17 https://scifaro.com/en/abs/archer-a-community-distributed-computing-infrastructure-for-computer-architecture-research-and-education-0807.17652015-05-13 https://scifaro.com/en/abs/an-adaptive-embedded-architecture-for-real-time-particle-image-velocimetry-algorithms-0807.37322008-07-24 https://scifaro.com/en/abs/on-transformations-of-load-store-maurer-instruction-set-architecture-0808.25842009-01-20 https://scifaro.com/en/abs/easily-testable-logical-networks-based-on-a-widened-long-flip-flop-0808.26022008-08-21 https://scifaro.com/en/abs/decting-errors-in-reversible-circuits-with-invariant-relationships-0812.38712008-12-22 https://scifaro.com/en/abs/a-high-dynamic-range-3-moduli-set-with-efficient-reverse-converter-0901.11232009-01-09 https://scifaro.com/en/abs/adaptive-fpga-noc-based-architecture-for-multispectral-image-correlation-0901.40812009-01-27 https://scifaro.com/en/abs/limit-on-the-addressability-of-fault-tolerant-nanowire-decoders-0901.46942009-01-30 https://scifaro.com/en/abs/crt-based-high-speed-parallel-architecture-for-long-bch-encoding-0904.31482009-04-22 https://scifaro.com/en/abs/hardware-trojan-by-hot-carrier-injection-0906.38322009-06-23 https://scifaro.com/en/abs/exploiting-semiconductor-properties-for-hardware-trojans-0906.38342009-06-23 https://scifaro.com/en/abs/hardware-virtualization-support-in-intel-amd-and-ibm-power-processors-0909.00992009-09-02 https://scifaro.com/en/abs/boosting-xml-filtering-with-a-scalable-fpga-based-architecture-0909.17812009-09-15 https://scifaro.com/en/abs/turbo-noc-a-framework-for-the-design-of-network-on-chip-based-turbo-decoder-architectures-0909.18762016-11-18 https://scifaro.com/en/abs/hard-data-on-soft-errors-a-large-scale-assessment-of-real-world-error-rates-in-gpgpu-0910.05052009-11-14 https://scifaro.com/en/abs/a-scalable-vlsi-architecture-for-soft-input-soft-output-depth-first-sphere-decoding-0910.34272015-03-13 https://scifaro.com/en/abs/a-fault-tolerant-structure-for-reliable-multi-core-systems-based-on-hardware-software-co-design-0910.37362016-09-08 https://scifaro.com/en/abs/virtual-threading-advanced-general-purpose-processors-architecture-0910.40522009-10-22 https://scifaro.com/en/abs/a-multicore-processor-based-real-time-system-for-automobile-management-application-1001.37162016-09-08 https://scifaro.com/en/abs/an-architectural-approach-for-decoding-and-distributing-functions-in-fpus-in-a-functional-processor-system-1001.37812016-09-08 https://scifaro.com/en/abs/maintaining-virtual-areas-on-fpgas-using-strip-packing-with-delays-1001.44932010-01-26 https://scifaro.com/en/abs/vlsi-architectures-for-wimax-channel-decoders-1001.46942010-01-27 https://scifaro.com/en/abs/evaluation-and-design-space-exploration-of-a-time-division-multiplexed-noc-on-fpga-for-image-analysis-applications-1002.18812010-02-10 https://scifaro.com/en/abs/ahb-compatible-ddr-sdram-controller-ip-core-for-arm-based-soc-1002.19532010-02-10 https://scifaro.com/en/abs/static-address-generation-easing-a-design-methodology-for-parallel-interleaver-architectures-1002.39902010-02-23 https://scifaro.com/en/abs/low-power-shift-and-add-multiplier-design-1006.11792010-07-15 https://scifaro.com/en/abs/fpga-implementation-of-a-reconfigurable-viterbi-decoder-for-wimax-receiver-1007.44652010-07-27 https://scifaro.com/en/abs/associative-control-processor-with-a-rigid-structure-1008.08382010-08-05 https://scifaro.com/en/abs/asynchronous-logic-circuits-and-sheaf-obstructions-1008.27292010-08-17 https://scifaro.com/en/abs/reversible-logic-synthesis-of-fault-tolerant-carry-skip-bcd-adder-1008.32882010-08-20 https://scifaro.com/en/abs/fault-tolerant-reversible-logic-synthesis-carry-look-ahead-and-carry-skip-adders-1008.33112010-08-20 https://scifaro.com/en/abs/synthesis-of-fault-tolerant-reversible-logic-circuits-1008.33402010-08-20 https://scifaro.com/en/abs/efficient-approaches-for-designing-fault-tolerant-reversible-carry-look-ahead-and-carry-skip-adders-1008.33442010-08-20 https://scifaro.com/en/abs/variable-block-carry-skip-logic-using-reversible-gates-1008.33522010-08-20 https://scifaro.com/en/abs/building-toffoli-network-for-reversible-logic-synthesis-based-on-swapping-bit-strings-1008.33572010-08-20 https://scifaro.com/en/abs/memristor-based-circuits-for-performing-basic-arithmetic-operations-1008.34522010-09-03 https://scifaro.com/en/abs/a-novel-quantum-cost-efficient-reversible-full-adder-gate-in-nanotechnology-1008.35332010-08-23 https://scifaro.com/en/abs/sorting-network-for-reversible-logic-synthesis-1008.36942010-08-24 https://scifaro.com/en/abs/bsssn-bit-string-swapping-sorting-network-for-reversible-logic-synthesis-1008.46682010-08-30 https://scifaro.com/en/abs/wideband-spectrum-sensing-at-sub-nyquist-rates-1009.13052010-09-08 https://scifaro.com/en/abs/power-optimized-programmable-embedded-controller-1009.17962010-09-10 https://scifaro.com/en/abs/on-the-design-and-analysis-of-quaternary-serial-and-parallel-adders-1009.26222010-09-15 https://scifaro.com/en/abs/fault-tolerant-variable-block-carry-skip-logic-vbcsl-using-parity-preserving-reversible-gates-1009.38192012-05-04 https://scifaro.com/en/abs/a-unique-10-segment-display-for-bengali-numerals-1009.45902010-09-27 https://scifaro.com/en/abs/universal-numeric-segmented-display-1009.49772010-09-28 https://scifaro.com/en/abs/multi-standard-programmable-baseband-modulator-for-next-generation-wireless-communication-1009.61322010-10-01 https://scifaro.com/en/abs/multiplierless-modules-for-forward-and-backward-integer-wavelet-transform-1010.40592021-08-20 https://scifaro.com/en/abs/hardware-architectures-for-successive-cancellation-decoding-of-polar-codes-1011.29192015-03-17 https://scifaro.com/en/abs/multi-core-adding-a-new-dimension-to-computing-1011.33822010-11-16 https://scifaro.com/en/abs/a-full-custom-asic-design-of-a-8-bit-25-mhz-pipeline-adc-using-0-35-um-cmos-technology-1011.41572012-07-25 https://scifaro.com/en/abs/systolic-arrays-for-lattice-reduction-aided-mimo-detection-1101.36982015-03-17 https://scifaro.com/en/abs/reversible-logic-based-concurrent-error-detection-methodology-for-emerging-nanocircuits-1101.42222011-01-24 https://scifaro.com/en/abs/risc-and-cisc-1101.53642013-02-22 https://scifaro.com/en/abs/a-simulation-experiment-on-a-built-in-self-test-equipped-with-pseudorandom-test-pattern-generator-and-multi-input-shift-register-misr-1102.08842011-02-07 https://scifaro.com/en/abs/a-secure-asynchronous-fpga-architecture-experimental-results-and-some-debug-feedback-1103.13602011-03-09 https://scifaro.com/en/abs/high-speed-multiple-valued-logic-full-adder-using-carbon-nano-tube-field-effect-transistor-1104.02982011-04-05 https://scifaro.com/en/abs/computer-arithmetic-preserving-hamming-distance-of-operands-in-operation-result-1104.33102011-04-19 https://scifaro.com/en/abs/improving-network-on-chip-based-turbo-decoder-architectures-1105.10142011-05-06 https://scifaro.com/en/abs/algebra-logical-repair-method-for-fpga-logic-blocks-1105.19672011-05-11 https://scifaro.com/en/abs/brain-like-infrastructure-for-embedded-soc-diagnosis-1105.19732016-11-18 https://scifaro.com/en/abs/a-flexible-ldpc-code-decoder-with-a-network-on-chip-as-underlying-interconnect-architecture-1105.26242011-05-16 https://scifaro.com/en/abs/multi-amdahl-optimal-resource-sharing-with-multiple-program-execution-segments-1105.29602011-05-17 https://scifaro.com/en/abs/hmtt-a-hybrid-hardware-software-tracing-system-for-bridging-memory-trace-s-semantic-gap-1106.25682011-06-15 https://scifaro.com/en/abs/pseudo-ring-testing-schemes-and-algorithms-of-ram-built-in-and-embedded-self-testing-1106.36772011-06-21 https://scifaro.com/en/abs/soc-software-components-diagnosis-technology-1106.36812016-11-17 https://scifaro.com/en/abs/reversible-arithmetic-logic-unit-1107.39242011-07-21 https://scifaro.com/en/abs/a-design-methodology-for-folded-pipelined-architectures-in-vlsi-applications-using-projective-space-lattices-1108.39702012-08-07 https://scifaro.com/en/abs/facile-algebraic-representation-of-a-novel-quaternary-logic-1108.54972017-12-21 https://scifaro.com/en/abs/a-novel-methodology-for-thermal-analysis-3-dimensional-memory-integration-1109.07082011-09-06 https://scifaro.com/en/abs/an-improved-distributed-routing-algorithm-for-benes-based-optical-noc-1109.07522011-09-06 https://scifaro.com/en/abs/intelligent-bees-for-qos-routing-in-networks-on-chip-1109.07552011-09-06 https://scifaro.com/en/abs/power-comparison-of-cmos-and-adiabatic-full-adder-circuit-1110.15492011-10-10 https://scifaro.com/en/abs/faster-energy-efficient-dadda-based-baugh-wooley-multipliers-1110.32812015-03-13 https://scifaro.com/en/abs/faster-and-low-power-twin-precision-multiplier-1110.33762011-10-20 https://scifaro.com/en/abs/multi-core-processors-an-overview-1110.35352011-10-18 https://scifaro.com/en/abs/optimal-final-carry-propagate-adder-design-for-parallel-multipliers-1110.35842011-10-18 https://scifaro.com/en/abs/accelerating-algorithms-using-a-dataflow-graph-in-a-reconfigurable-system-1110.36552015-03-13 https://scifaro.com/en/abs/fpga-implementation-of-short-critical-path-cordic-based-approximation-of-the-eight-point-dct-1110.68652011-11-01 https://scifaro.com/en/abs/efficient-network-for-non-binary-qc-ldpc-decoder-1111.07032011-11-04 https://scifaro.com/en/abs/reduced-latency-sc-polar-decoder-architectures-1111.07042011-11-04 https://scifaro.com/en/abs/low-latency-sc-decoder-architectures-for-polar-codes-1111.07052011-11-04 https://scifaro.com/en/abs/design-and-simulation-of-an-8-bit-dedicated-processor-for-calculating-the-sine-and-cosine-of-an-angle-using-the-cordic-algorithm-1111.10862017-04-07 https://scifaro.com/en/abs/performance-of-cache-memory-subsystems-for-multicore-architectures-1111.30562011-11-15 https://scifaro.com/en/abs/elastic-fidelity-trading-off-computational-accuracy-for-energy-reduction-1111.42792011-11-22 https://scifaro.com/en/abs/hardware-implementation-of-successive-cancellation-decoders-for-polar-codes-1111.43622015-03-19 https://scifaro.com/en/abs/a-new-design-for-array-multiplier-with-trade-off-in-power-and-area-1111.72582011-12-01 https://scifaro.com/en/abs/quantum-cost-efficient-reversible-bcd-adder-for-nanotechnology-based-systems-1112.07272012-05-04 https://scifaro.com/en/abs/information-analysis-infrastructure-for-diagnosis-1201.09542012-01-05 https://scifaro.com/en/abs/theoretical-modeling-and-simulation-of-phase-locked-loop-pll-for-clock-data-recovery-cdr-1201.16742012-01-10 https://scifaro.com/en/abs/design-and-asic-implementation-of-duc-ddc-for-communication-systems-1201.21072012-03-12 https://scifaro.com/en/abs/an-efficient-fpga-implementation-of-mri-image-filtering-and-tumor-characterization-using-xilinx-system-generator-1201.25422012-01-13 https://scifaro.com/en/abs/a-resolution-for-shared-memory-conflict-in-multiprocessor-system-on-a-chip-1202.06132012-02-06 https://scifaro.com/en/abs/a-handy-systematic-method-for-data-hazards-detection-in-an-instruction-set-of-a-pipelined-microprocessor-1203.07872012-03-06 https://scifaro.com/en/abs/the-distributed-network-processor-a-novel-off-chip-and-on-chip-interconnection-network-architecture-1203.15362012-03-08 https://scifaro.com/en/abs/designing-a-wishbone-protocol-network-adapter-for-an-asynchronous-network-on-chip-1203.41502012-03-20 https://scifaro.com/en/abs/locke-detailed-specification-tables-1203.53492012-03-27 https://scifaro.com/en/abs/c-slow-technique-vs-multiprocessor-in-designing-low-area-customized-instruction-set-processor-for-embedded-applications-1204.11792012-04-06 https://scifaro.com/en/abs/effect-of-thread-level-parallelism-on-the-performance-of-optimum-architecture-for-embedded-applications-1204.27722012-04-13 https://scifaro.com/en/abs/performance-optimum-superscalar-architecture-for-embedded-applications-1204.28092012-04-13 https://scifaro.com/en/abs/reversible-programmable-logic-array-rpla-using-feynman-mux-gates-for-low-power-industrial-applications-1204.54072012-04-25 https://scifaro.com/en/abs/a-simple-1-byte-1-clock-rc4-design-and-its-efficient-implementation-in-fpga-coprocessor-for-secured-ethernet-communication-1205.17372012-07-30 https://scifaro.com/en/abs/wishbone-bus-architecture-a-survey-and-comparison-1205.18602012-05-10 https://scifaro.com/en/abs/microcontroller-based-testing-of-digital-ip-core-1205.18662012-05-10 https://scifaro.com/en/abs/design-space-exploration-to-find-the-optimum-cache-and-register-file-size-for-embedded-applications-1205.18712012-05-10 https://scifaro.com/en/abs/design-and-implementation-of-real-time-aes-128-on-real-time-operating-system-for-multiple-fpga-communication-1205.21532012-05-11 https://scifaro.com/en/abs/relaxed-half-stochastic-belief-propagation-1205.24282012-05-14 https://scifaro.com/en/abs/investigating-warp-size-impact-in-gpus-1205.49672012-05-23 https://scifaro.com/en/abs/architecture-for-real-time-continuous-sorting-on-large-width-data-volume-for-fpga-based-applications-1206.15672012-06-08 https://scifaro.com/en/abs/reptfd-replay-based-transient-fault-detection-1206.21322012-06-12 https://scifaro.com/en/abs/dls-directoryless-shared-last-level-cache-1206.47532012-10-09 https://scifaro.com/en/abs/the-necessity-for-hardware-qos-support-for-server-consolidation-and-cloud-computing-1206.62132012-06-28 https://scifaro.com/en/abs/dynamic-priority-queue-an-sdram-arbiter-with-bounded-access-latencies-for-tight-wcet-calculation-1207.11872015-03-20 https://scifaro.com/en/abs/design-and-development-of-low-cost-multi-channel-usb-data-1207.16832012-07-10 https://scifaro.com/en/abs/design-of-pic12f675-microcontroller-based-data-acquisition-system-for-slowly-varying-signals-1207.20602012-07-10 https://scifaro.com/en/abs/low-cost-pc-based-real-time-data-logging-system-using-pcs-parallel-port-for-slowly-varying-signals-1207.27392012-07-12 https://scifaro.com/en/abs/design-and-performance-analysis-of-hybrid-adders-for-high-speed-arithmetic-circuit-1207.28402012-07-13 https://scifaro.com/en/abs/ethernet-packet-processor-for-soc-application-1207.51382012-07-24 https://scifaro.com/en/abs/design-and-implementation-of-a-digital-clock-showing-digits-in-bangla-font-using-microcontroller-at89c4051-1208.09952012-08-07 https://scifaro.com/en/abs/dynamic-warp-resizing-in-high-performance-simt-1208.23742012-11-06 https://scifaro.com/en/abs/a-cache-management-strategy-to-replace-wear-leveling-techniques-for-embedded-flash-memory-1209.30992012-09-17 https://scifaro.com/en/abs/deadlock-recovery-technique-in-bus-enhanced-noc-architecture-1209.35642012-09-18 https://scifaro.com/en/abs/emulating-a-large-memory-with-a-collection-of-small-ones-1210.11582015-11-17 https://scifaro.com/en/abs/a-ternary-digital-to-analog-converter-with-high-power-output-and-170-db-dynamic-range-1210.63382012-10-24 https://scifaro.com/en/abs/design-of-a-reconfigurable-dsp-processor-with-bit-efficient-residue-number-system-1211.52482012-11-26 https://scifaro.com/en/abs/design-and-implementation-of-multistage-interconnection-networks-for-soc-networks-1212.03102012-12-04 https://scifaro.com/en/abs/a-brief-experience-on-journey-through-hardware-developments-for-image-processing-and-its-applications-on-cryptography-1212.63032013-01-14 https://scifaro.com/en/abs/mims-towards-a-message-interface-based-memory-system-1301.00512014-04-10 https://scifaro.com/en/abs/a-joint-communication-and-application-simulator-for-noc-based-socs-1301.14652013-06-03 https://scifaro.com/en/abs/reconfiguration-strategies-for-online-hardware-multitasking-in-embedded-systems-1301.32812013-01-16 https://scifaro.com/en/abs/mgsim-simulation-tools-for-multi-core-processor-architectures-1302.13902013-02-07 https://scifaro.com/en/abs/reduction-in-packet-delay-through-the-use-of-common-buffer-over-distributed-buffer-in-the-routing-node-of-noc-architecture-1302.41722013-02-19 https://scifaro.com/en/abs/a-low-power-content-addressable-memory-based-on-clustered-sparse-networks-1302.44632016-11-17 https://scifaro.com/en/abs/dynamic-power-reduction-in-a-novel-cmos-5t-sram-for-low-power-soc-1302.44642013-02-20 https://scifaro.com/en/abs/hybrid-crossbar-architecture-for-a-memristor-based-memory-1302.65152013-04-10 https://scifaro.com/en/abs/an-efficient-cntfet-based-7-input-minority-gate-1303.21752013-03-12 https://scifaro.com/en/abs/on-whether-and-how-d-risc-and-microgrids-can-be-kept-relevant-self-assessment-report-1303.48922013-03-21 https://scifaro.com/en/abs/object-oriented-approach-to-rapid-custom-instruction-design-1303.57622016-11-15 https://scifaro.com/en/abs/improved-analytical-delay-models-for-rc-coupled-interconnects-1304.08352013-04-04 https://scifaro.com/en/abs/open-tiled-manycore-system-on-chip-1304.50812013-04-19 https://scifaro.com/en/abs/a-formalisation-of-xmas-1304.78622013-05-01 https://scifaro.com/en/abs/phase-priority-based-directory-coherence-for-multicore-processor-1305.30382013-05-15 https://scifaro.com/en/abs/a-novel-reconfigurable-architecture-of-a-dsp-processor-for-efficient-mapping-of-dsp-functions-using-field-programmable-dsp-arrays-1306.00892013-06-04 https://scifaro.com/en/abs/an-improved-structure-of-reversible-adder-and-subtractor-1306.18892013-06-11 https://scifaro.com/en/abs/computer-architecture-with-associative-processor-replacing-last-level-cache-and-simd-accelerator-1306.31092013-11-11 https://scifaro.com/en/abs/the-effect-of-communication-and-synchronization-on-amdahl-law-in-multicore-systems-1306.33022013-06-17 https://scifaro.com/en/abs/a-wrapper-of-pci-express-with-fifo-interfaces-based-on-fpga-1306.55012013-06-25 https://scifaro.com/en/abs/power-efficient-carry-propagate-adder-1307.33242013-07-15 https://scifaro.com/en/abs/design-of-parity-preserving-logic-based-fault-tolerant-reversible-arithmetic-logic-unit-1307.36902013-07-16 https://scifaro.com/en/abs/thermal-analysis-of-3d-associative-processor-1307.38532013-07-16 https://scifaro.com/en/abs/relative-performance-of-a-multi-level-cache-with-last-level-cache-replacement-an-analytic-review-1307.64062013-07-25 https://scifaro.com/en/abs/fast-polar-decoders-algorithm-and-implementation-1307.71542015-05-20 https://scifaro.com/en/abs/allocating-the-chains-of-consecutive-additions-for-optimal-fixed-point-data-path-synthesis-1307.83192013-08-01 https://scifaro.com/en/abs/fpsynt-a-fixed-point-datapath-synthesis-tool-for-embedded-systems-1307.84012013-08-01 https://scifaro.com/en/abs/designing-parity-preserving-reversible-circuits-1308.08402013-08-06 https://scifaro.com/en/abs/selective-decoding-in-associative-memories-based-on-sparse-clustered-networks-1308.60212016-11-15 https://scifaro.com/en/abs/low-power-area-designs-of-1bit-full-adder-in-cadence-virtuoso-platform-1309.24582013-09-11 https://scifaro.com/en/abs/evaluation-of-the-performance-energy-overhead-in-dsp-video-decoding-and-its-implications-1309.25332013-09-11 https://scifaro.com/en/abs/on-the-performance-potential-of-speculative-execution-based-on-branch-and-value-prediction-1309.36852013-09-17 https://scifaro.com/en/abs/energy-saving-techniques-for-phase-change-memory-pcm-1309.37852013-09-17 https://scifaro.com/en/abs/advances-in-computer-architecture-1309.54592013-09-24 https://scifaro.com/en/abs/microgrid-the-microthreaded-many-core-architecture-1309.55072013-09-24 https://scifaro.com/en/abs/design-space-exploration-in-the-microthreaded-many-core-architecture-1309.55512013-09-24 https://scifaro.com/en/abs/a-cache-coloring-based-technique-for-saving-leakage-energy-in-multitasking-systems-1309.56472013-09-24 https://scifaro.com/en/abs/a-cache-reconfiguration-approach-for-saving-leakage-and-refresh-energy-in-embedded-dram-caches-1309.70822013-09-30 https://scifaro.com/en/abs/a-low-voltage-low-power-4-bit-bcd-adder-designed-using-the-clock-gated-power-gating-and-the-dvt-scheme-1309.71632016-11-18 https://scifaro.com/en/abs/recycled-error-bits-energy-efficient-architectural-support-for-higher-precision-floating-point-1309.73212013-09-30 https://scifaro.com/en/abs/partial-sums-generation-architecture-for-successive-cancellation-decoding-of-polar-codes-1309.78182015-01-12 https://scifaro.com/en/abs/technical-report-functional-constraint-extraction-from-register-transfer-level-for-atpg-1310.01002013-10-02 https://scifaro.com/en/abs/janus-ii-a-new-generation-application-driven-computer-for-spin-system-simulations-1310.10322013-12-03 https://scifaro.com/en/abs/partial-sums-computation-in-polar-codes-decoding-1310.17122015-01-12 https://scifaro.com/en/abs/a-novel-reconfigurable-computing-architecture-for-image-signal-processing-using-circuit-switched-noc-and-synchronous-dataflow-model-1310.33562013-10-15 https://scifaro.com/en/abs/dynamic-cache-reconfiguration-based-techniques-for-improving-cache-energy-efficiency-1310.42312013-10-17 https://scifaro.com/en/abs/evaluating-cache-coherent-shared-virtual-memory-for-heterogeneous-multicore-chips-1310.77922013-10-30 https://scifaro.com/en/abs/using-cache-coloring-to-mitigate-inter-set-write-variation-in-non-volatile-caches-1310.84942013-11-01 https://scifaro.com/en/abs/a-technique-for-write-endurance-aware-management-of-resistive-ram-last-level-caches-1311.00412014-05-01 https://scifaro.com/en/abs/a-technique-for-efficiently-managing-sram-nvm-hybrid-cache-1311.01702013-11-04 https://scifaro.com/en/abs/input-output-logic-based-fault-tolerant-design-technique-for-sram-based-fpgas-1311.06022013-11-06 https://scifaro.com/en/abs/3d-cache-hierarchy-optimization-1311.16672013-11-08 https://scifaro.com/en/abs/architectural-improvements-and-28-nm-fpga-implementation-of-the-apenet-3d-torus-network-for-hybrid-hpc-systems-1311.17412015-06-17 https://scifaro.com/en/abs/row-based-dual-vdd-assignment-for-a-level-converter-free-csa-design-and-its-near-threshold-operation-1312.08852014-10-07 https://scifaro.com/en/abs/a-cache-energy-optimization-technique-for-stt-ram-last-level-cache-1312.22072014-08-12 https://scifaro.com/en/abs/a-survey-of-network-on-chip-tools-1312.29762013-12-13 https://scifaro.com/en/abs/a-survey-of-techniques-for-improving-energy-efficiency-in-embedded-computing-systems-1401.07652014-01-07 https://scifaro.com/en/abs/on-the-likelihood-of-multiple-bit-upsets-in-logic-circuits-1401.10032014-01-07 https://scifaro.com/en/abs/hardware-implementation-of-four-byte-per-clock-rc4-algorithm-1401.27272014-01-14 https://scifaro.com/en/abs/fault-detection-for-rc4-algorithm-and-its-implementation-on-fpga-platform-1401.27322016-10-31 https://scifaro.com/en/abs/design-of-novel-architectures-and-field-programmable-gate-arrays-implementation-of-two-dimensional-gaussian-surround-function-1401.27682014-01-14 https://scifaro.com/en/abs/performance-evaluation-of-ecc-in-single-and-multi-processor-architectures-on-fpga-based-embedded-system-1401.34212014-02-20 https://scifaro.com/en/abs/hermes-a-hierarchical-broadcast-based-silicon-photonic-interconnect-for-scalable-many-core-systems-1401.46292014-01-21 https://scifaro.com/en/abs/the-design-of-a-network-on-chip-architecture-based-on-an-avionic-protocol-1401.48912014-01-21 https://scifaro.com/en/abs/design-of-a-high-speed-xaui-based-on-dynamic-reconfigurable-transceiver-ip-core-1401.63702014-01-27 https://scifaro.com/en/abs/design-of-an-encryption-decryption-module-oriented-for-internet-information-security-soc-design-1401.63752014-01-27 https://scifaro.com/en/abs/reversible-squaring-circuit-for-low-power-digital-signal-processing-1402.24152014-12-18 https://scifaro.com/en/abs/l-shape-based-layout-fracturing-for-e-beam-lithography-1402.24202014-02-12 https://scifaro.com/en/abs/triple-patterning-lithography-tpl-layout-decomposition-using-end-cutting-1402.24252014-02-12 https://scifaro.com/en/abs/e-blow-e-beam-lithography-overlapping-aware-stencil-planning-for-mcc-system-1402.24352014-02-12 https://scifaro.com/en/abs/self-aligned-double-patterning-friendly-configuration-for-standard-cell-library-considering-placement-1402.24422014-02-12 https://scifaro.com/en/abs/layout-decomposition-for-triple-patterning-lithography-1402.24592014-02-12 https://scifaro.com/en/abs/network-flow-based-simultaneous-retiming-and-slack-budgeting-for-low-power-design-1402.24602014-02-12 https://scifaro.com/en/abs/floorplanning-and-topology-generation-for-application-specific-network-on-chip-1402.24622014-02-12 https://scifaro.com/en/abs/design-and-implementation-of-bit-transition-counter-1402.25362014-02-12 https://scifaro.com/en/abs/methodology-for-standard-cell-compliance-and-detailed-placement-for-triple-patterning-lithography-1402.26352014-02-12 https://scifaro.com/en/abs/a-high-performance-triple-patterning-layout-decomposer-with-balanced-density-1402.28902014-02-13 https://scifaro.com/en/abs/multi-voltage-and-level-shifter-assignment-driven-floorplanning-1402.28942014-02-13 https://scifaro.com/en/abs/glow-a-global-router-for-low-power-thermal-reliable-interconnect-synthesis-using-photonic-wavelength-multiplexing-1402.28992014-02-13 https://scifaro.com/en/abs/epic-efficient-prediction-of-ic-manufacturing-hotspots-with-a-unified-meta-classification-formulation-1402.29042014-02-13 https://scifaro.com/en/abs/triad-a-triple-patterning-lithography-aware-detailed-router-1402.29062014-02-14 https://scifaro.com/en/abs/voltage-and-level-shifter-assignment-driven-floorplanning-1402.31492014-02-14 https://scifaro.com/en/abs/lithography-hotspot-detection-and-mitigation-in-nanometer-vlsi-1402.31502014-02-14 https://scifaro.com/en/abs/open-cores-for-digital-signal-processing-1402.60052014-02-26 https://scifaro.com/en/abs/five-modular-redundancy-with-mitigation-technique-to-recover-the-error-module-1403.19282014-03-11 https://scifaro.com/en/abs/development-of-syrec-based-expandable-reversible-logic-circuits-1403.26862014-03-12 https://scifaro.com/en/abs/state-dependent-statistical-timing-model-for-voltage-scaled-circuits-1403.27852014-03-13 https://scifaro.com/en/abs/a-flexible-design-for-optimization-of-hardware-architecture-in-distributed-arithmetic-based-fir-filters-1403.45542014-03-19 https://scifaro.com/en/abs/design-space-exploration-tools-for-the-byorisc-configurable-processor-family-1403.66322014-03-27 https://scifaro.com/en/abs/instruction-set-selection-for-multi-application-based-asip-design-an-instruction-level-study-1403.72912014-03-31 https://scifaro.com/en/abs/heterogeneous-processor-pipeline-for-a-product-cipher-application-1403.72992014-03-31 https://scifaro.com/en/abs/generating-and-evaluating-application-specific-hardware-extensions-1403.73802014-03-31 https://scifaro.com/en/abs/comments-on-ieee-1588-clock-synchronization-using-dual-slave-clocks-in-a-slave-1404.13112016-02-02 https://scifaro.com/en/abs/a-high-level-model-of-embedded-flash-energy-consumption-1404.16022014-12-05 https://scifaro.com/en/abs/a-signal-processor-for-gaussian-message-passing-1404.31622014-04-14 https://scifaro.com/en/abs/modeling-the-temperature-bias-of-power-consumption-for-nanometer-scale-cpus-in-application-processors-1404.33812014-04-15 https://scifaro.com/en/abs/design-space-exploration-for-image-processing-architectures-on-fpga-targets-1404.38772014-04-16 https://scifaro.com/en/abs/a-survey-of-methods-for-analyzing-and-improving-gpu-energy-efficiency-1404.46292014-04-21 https://scifaro.com/en/abs/hardware-efficient-wimax-deinterleaver-capable-of-address-generation-for-random-interleaving-depths-1404.58852014-04-24 https://scifaro.com/en/abs/fpga-design-of-a-cdma2000-turbo-decoder-1404.59292014-04-24 https://scifaro.com/en/abs/multiplierless-approximate-4-point-dct-vlsi-architectures-for-transform-block-coding-1405.04132014-05-05 https://scifaro.com/en/abs/massively-parallel-processor-architectures-for-resource-aware-computing-1405.29072014-05-14 https://scifaro.com/en/abs/emulated-asic-power-and-temperature-monitor-system-for-fpga-prototyping-of-an-invasive-mpsoc-computing-architecture-1405.29092014-05-14 https://scifaro.com/en/abs/architectural-design-of-a-ram-arbiter-1405.42322014-05-21 https://scifaro.com/en/abs/modeling-algorithms-in-systemc-and-acl2-1406.15652014-06-09 https://scifaro.com/en/abs/the-z1-architecture-and-algorithms-of-konrad-zuse-s-first-computer-1406.18862025-08-18 https://scifaro.com/en/abs/an-efficient-synchronous-static-memory-design-for-embedded-system-1406.46282014-06-19 https://scifaro.com/en/abs/application-specific-cache-simulation-analysis-for-application-specific-instruction-set-processor-1406.50002014-06-20 https://scifaro.com/en/abs/preemptive-thread-block-scheduling-with-online-structural-runtime-prediction-for-concurrent-gpgpu-kernels-1406.60372014-06-25 https://scifaro.com/en/abs/selective-match-line-energizer-content-addressable-memory-smle-cam-1406.76622014-07-01 https://scifaro.com/en/abs/application-specific-hardware-design-simulation-for-high-performance-embedded-system-1407.01472014-07-02 https://scifaro.com/en/abs/fpga-based-efficient-multiplier-for-image-processing-applications-using-recursive-error-free-mitchell-log-multiplier-and-kom-architecture-1407.20822014-07-09 https://scifaro.com/en/abs/an-ecg-soc-with-535nw-channel-lossless-data-compression-for-wearable-sensors-1407.51732014-07-22 https://scifaro.com/en/abs/modeling-and-simulation-of-multiprocessor-systems-mpsoc-by-systemc-tlm2-1408.09822014-08-06 https://scifaro.com/en/abs/proceedings-of-the-first-international-workshop-on-fpgas-for-software-programmers-fsp-2014-1408.44232015-03-02 https://scifaro.com/en/abs/a-many-core-overlay-for-high-performance-embedded-computing-on-fpgas-1408.54012014-08-25 https://scifaro.com/en/abs/design-of-novel-algorithm-and-architecture-for-gaussian-based-color-image-enhancement-system-for-real-time-applications-1409.40432014-09-16 https://scifaro.com/en/abs/an-efficient-list-decoder-architecture-for-polar-codes-1409.47442014-11-18 https://scifaro.com/en/abs/an-ecg-on-chip-with-535-nw-channel-integrated-lossless-data-compressor-for-wireless-sensors-1409.80182014-09-30 https://scifaro.com/en/abs/an-ecg-on-chip-for-wearable-cardiac-monitoring-devices-1409.80202014-09-30 https://scifaro.com/en/abs/on-metric-sorting-for-successive-cancellation-list-decoding-of-polar-codes-1410.44602016-02-15 https://scifaro.com/en/abs/multi-core-ssl-tls-security-processor-architecture-prototype-design-with-automated-preferential-algorithm-in-fpga-1410.75602016-11-25 https://scifaro.com/en/abs/programming-the-adapteva-epiphany-64-core-network-on-chip-coprocessor-1410.87722014-11-03 https://scifaro.com/en/abs/inner-loop-optimizations-in-mapping-single-threaded-programs-to-hardware-1411.08632014-11-05 https://scifaro.com/en/abs/energy-efficient-full-adder-cell-design-with-using-carbon-nanotube-field-effect-transistors-in-32-nanometer-technology-1411.20882014-11-11 https://scifaro.com/en/abs/designing-high-speed-low-power-full-adder-cells-based-on-carbon-nanotube-technology-1411.22122014-11-11 https://scifaro.com/en/abs/fast-prefix-adders-for-non-uniform-input-arrival-times-1411.29172014-11-12 https://scifaro.com/en/abs/evaluation-of-silicon-consumption-for-a-connectionless-network-on-chip-1411.34922014-11-14 https://scifaro.com/en/abs/analog-signal-processing-solution-for-image-alignment-1411.39292014-11-17 https://scifaro.com/en/abs/correction-to-the-2005-paper-digit-selection-for-srt-division-and-square-root-1411.64982014-11-25 https://scifaro.com/en/abs/sphynx-a-shared-instruction-cache-exporatory-study-1412.11402014-12-04 https://scifaro.com/en/abs/performance-enhancement-of-routers-in-networks-on-chip-using-dynamic-virtual-channels-allocation-1412.29502014-12-10 https://scifaro.com/en/abs/prophet-a-speculative-multi-threading-execution-model-with-architectural-support-based-on-cmp-1412.32242015-12-29 https://scifaro.com/en/abs/a-high-throughput-energy-efficient-implementation-of-successive-cancellation-decoder-for-polar-codes-using-combinational-logic-1412.38292016-01-12 https://scifaro.com/en/abs/kickstarting-high-performance-energy-efficient-manycore-architectures-with-epiphany-1412.55382014-12-18 https://scifaro.com/en/abs/a-237-gbps-unrolled-hardware-polar-decoder-1412.60432015-05-20 https://scifaro.com/en/abs/a-feasibility-study-on-programmer-specific-instruction-set-processors-psisps-1412.76922014-12-25 https://scifaro.com/en/abs/a-model-study-of-an-all-digital-discrete-time-and-embedded-linear-regulator-1501.005792015-01-06 https://scifaro.com/en/abs/design-of-a-transport-triggered-architecture-processor-for-flexible-iterative-turbo-decoder-1501.041922015-01-20 https://scifaro.com/en/abs/tejas-simulator-validation-against-hardware-1501.074202015-01-30 https://scifaro.com/en/abs/running-identical-threads-in-c-slow-retiming-based-designs-for-functional-failure-detection-1502.012372015-02-05 https://scifaro.com/en/abs/a-high-performance-solid-state-disk-with-double-data-rate-nand-flash-memory-1502.022392015-02-10 https://scifaro.com/en/abs/a-row-parallel-8-times-8-2-d-dct-architecture-using-algebraic-integer-based-exact-computation-1502.042212015-02-17 https://scifaro.com/en/abs/a-novel-architecture-of-area-efficient-fft-algorithm-for-fpga-implementation-1502.070552015-02-26 https://scifaro.com/en/abs/proceedings-of-the-date-friday-workshop-on-heterogeneous-architectures-and-design-methods-for-embedded-image-systems-his-2015-1502.072412015-02-27 https://scifaro.com/en/abs/generation-and-validation-of-custom-multiplication-ip-blocks-from-the-web-1502.074542015-02-27 https://scifaro.com/en/abs/a-general-scheme-for-noise-tolerant-logic-design-based-on-probabilistic-and-dcvs-approaches-1503.023542015-03-10 https://scifaro.com/en/abs/strategies-for-high-throughput-fpga-based-qc-ldpc-decoder-architecture-1503.029862015-05-12 https://scifaro.com/en/abs/design-of-high-performance-mips-cryptography-processor-based-on-t-des-algorithm-1503.031662015-03-12 https://scifaro.com/en/abs/dynamic-partitioning-of-physical-memory-among-virtual-machines-asmi-architectural-support-for-memory-isolation-1503.031692018-05-11 https://scifaro.com/en/abs/logic-bist-state-of-the-art-and-open-problems-1503.046282015-03-17 https://scifaro.com/en/abs/improving-gpu-performance-through-resource-sharing-1503.056942015-06-08 https://scifaro.com/en/abs/binary-adder-circuits-of-asymptotically-minimum-depth-linear-size-and-fan-out-two-1503.086592017-01-19 https://scifaro.com/en/abs/low-latency-list-decoding-of-polar-codes-with-double-thresholding-1504.034372015-11-30 https://scifaro.com/en/abs/migrantstore-leveraging-virtual-memory-in-dram-pcm-memory-architecture-1504.042972015-04-17 https://scifaro.com/en/abs/a-reconfigurable-vector-instruction-processor-for-accelerating-a-convection-parametrization-model-on-fpgas-1504.045862015-04-20 https://scifaro.com/en/abs/multi-mode-unrolled-architectures-for-polar-decoders-1505.014592016-07-12 https://scifaro.com/en/abs/tpad-hardware-trojan-prevention-and-detection-for-trusted-integrated-circuits-1505.022112016-11-18 https://scifaro.com/en/abs/twin-load-building-a-scalable-memory-system-over-the-non-scalable-interface-1505.034762015-05-14 https://scifaro.com/en/abs/an-approach-to-data-prefetching-using-2-dimensional-selection-criteria-1505.038992015-05-18 https://scifaro.com/en/abs/a-2-48gb-s-qc-ldpc-decoder-implementation-on-the-ni-usrp-2953r-1505.043392015-05-19 https://scifaro.com/en/abs/high-speed-fault-tolerant-secure-communication-for-muon-chamber-using-fpga-based-gbt-emulator-1505.045692016-01-20 https://scifaro.com/en/abs/squash-simple-qos-aware-high-performance-memory-scheduler-for-heterogeneous-systems-with-hardware-accelerators-1505.075022015-05-29 https://scifaro.com/en/abs/simultaneous-multi-layer-access-a-high-bandwidth-and-low-cost-3d-stacked-memory-interface-1506.031602015-06-11 https://scifaro.com/en/abs/dew-a-fast-level-1-cache-simulation-approach-for-embedded-processors-with-fifo-replacement-policy-1506.031812015-09-01 https://scifaro.com/en/abs/trishul-a-single-pass-optimal-two-level-inclusive-data-cache-hierarchy-selection-process-for-real-time-mpsocs-1506.031822015-09-01 https://scifaro.com/en/abs/ciparsim-cache-intersection-property-assisted-rapid-single-pass-fifo-cache-simulation-technique-1506.031862015-09-01 https://scifaro.com/en/abs/accelerating-non-volatile-hybrid-processor-cache-design-space-exploration-for-application-specific-embedded-systems-1506.031932015-09-01 https://scifaro.com/en/abs/fpga-based-novel-high-speed-daq-system-design-with-error-correction-1507.017772015-07-08 https://scifaro.com/en/abs/managing-hybrid-main-memories-with-a-page-utility-driven-performance-model-1507.033032019-12-18 https://scifaro.com/en/abs/proceedings-of-the-second-international-workshop-on-fpgas-for-software-programmers-fsp-2015-1508.063202015-08-27 https://scifaro.com/en/abs/model-based-hardware-design-for-fpgas-using-folding-transformations-based-on-subcircuits-1508.068112015-08-28 https://scifaro.com/en/abs/designing-hardware-software-systems-for-embedded-high-performance-computing-1508.068322015-08-28 https://scifaro.com/en/abs/proposal-of-ros-compliant-fpga-component-for-low-power-robotic-systems-1508.071232015-08-31 https://scifaro.com/en/abs/performance-monitoring-for-multicore-embedded-computing-systems-on-fpgas-1508.071262015-08-31 https://scifaro.com/en/abs/virtualization-architecture-for-noc-based-reconfigurable-systems-1508.071272015-08-31 https://scifaro.com/en/abs/using-system-hyper-pipelining-shp-to-improve-the-performance-of-a-coarse-grained-reconfigurable-architecture-cgra-mapped-on-an-fpga-1508.071392015-08-31 https://scifaro.com/en/abs/dsl-based-design-space-exploration-for-temporal-and-spatial-parallelism-of-custom-stream-computing-1509.000402015-09-02 https://scifaro.com/en/abs/automatic-nested-loop-acceleration-on-fpgas-using-soft-cgra-overlay-1509.000422015-09-02 https://scifaro.com/en/abs/dissecting-gpu-memory-hierarchy-through-microbenchmarking-1509.023082016-03-15 https://scifaro.com/en/abs/fpga-implementation-of-high-speed-baugh-wooley-multiplier-using-decomposition-logic-1509.035752015-09-14 https://scifaro.com/en/abs/dream-dynamic-re-arrangement-of-address-mapping-to-improve-the-performance-of-drams-1509.037212015-09-15 https://scifaro.com/en/abs/happy-hybrid-address-based-page-policy-in-drams-1509.037402015-09-15 https://scifaro.com/en/abs/feasible-methodology-for-optimization-of-a-novel-reversible-binary-compressor-1509.042402015-09-15 https://scifaro.com/en/abs/high-speed-vlsi-architecture-for-3-d-discrete-wavelet-transform-1509.042682015-09-16 https://scifaro.com/en/abs/cost-efficient-design-of-reversible-adder-circuits-for-low-power-applications-1509.046182015-09-16 https://scifaro.com/en/abs/a-novel-method-for-soft-error-mitigation-in-fpga-using-adaptive-cross-parity-code-1509.068912015-09-24 https://scifaro.com/en/abs/automatic-latency-balancing-in-vhdl-implemented-complex-pipelined-systems-1509.081112015-11-24 https://scifaro.com/en/abs/in-field-logic-repair-of-deep-sub-micron-cmos-processors-1509.092492015-10-07 https://scifaro.com/en/abs/a-high-throughput-list-decoder-architecture-for-polar-codes-1510.025742016-11-17 https://scifaro.com/en/abs/a-clock-synchronizer-for-repeaterless-low-swing-on-chip-links-1510.042412015-10-15 https://scifaro.com/en/abs/network-on-chip-with-load-balancing-based-on-interleave-of-flits-technique-1510.067912015-10-26 https://scifaro.com/en/abs/secured-a-secure-dual-core-embedded-processor-1511.019462015-11-09 https://scifaro.com/en/abs/testable-design-of-repeaterless-low-swing-on-chip-interconnect-1511.067262015-11-23 https://scifaro.com/en/abs/tardis-2-0-optimized-time-traveling-coherence-for-relaxed-consistency-models-1511.087742016-07-28 https://scifaro.com/en/abs/digital-ldo-with-time-interleaved-comparators-for-fast-response-and-low-ripple-1511.090742015-12-01 https://scifaro.com/en/abs/efficient-edge-detection-on-low-cost-fpgas-1512.005042015-12-03 https://scifaro.com/en/abs/partitioned-successive-cancellation-list-decoding-of-polar-codes-1512.031282017-03-28 https://scifaro.com/en/abs/configurable-memory-systems-for-embedded-many-core-processors-1601.008942016-01-08 https://scifaro.com/en/abs/design-of-a-low-power-1-65-gbps-data-channel-for-hdmi-transmitter-1601.014632016-01-08 https://scifaro.com/en/abs/profiling-assisted-decoupled-access-execute-1601.017222016-01-11 https://scifaro.com/en/abs/reducing-performance-impact-of-dram-refresh-by-parallelizing-refreshes-with-accesses-1601.063522016-01-26 https://scifaro.com/en/abs/tiered-latency-dram-tl-dram-1601.069032016-01-27 https://scifaro.com/en/abs/enabling-efficient-dynamic-resizing-of-large-dram-caches-via-a-hardware-consistent-hashing-mechanism-1602.007222016-02-03 https://scifaro.com/en/abs/effect-of-data-sharing-on-private-cache-design-in-chip-multiprocessors-1602.013292016-02-04 https://scifaro.com/en/abs/a-framework-for-accelerating-bottlenecks-in-gpu-execution-with-assist-warps-1602.013482016-02-04 https://scifaro.com/en/abs/fpga-based-implementation-of-deep-neural-networks-using-on-chip-memory-only-1602.016162016-08-30 https://scifaro.com/en/abs/energy-efficient-video-fusion-with-heterogeneous-cpu-fpga-devices-1602.025172016-02-09 https://scifaro.com/en/abs/fpga-hardware-acceleration-of-monte-carlo-simulations-for-the-ising-model-1602.030162016-02-10 https://scifaro.com/en/abs/openrisc-system-on-chip-design-emulation-1602.030952016-02-10 https://scifaro.com/en/abs/dark-memory-and-accelerator-rich-system-optimization-in-the-dark-silicon-era-1602.041832017-06-06 https://scifaro.com/en/abs/temperature-aware-dynamic-optimization-of-embedded-systems-1602.044142016-02-16 https://scifaro.com/en/abs/phase-distance-mapping-a-phase-based-cache-tuning-methodology-for-embedded-systems-1602.044152016-02-16 https://scifaro.com/en/abs/a-dynamic-overlay-supporting-just-in-time-assembly-to-construct-customized-hardware-accelerators-1603.011872016-03-04 https://scifaro.com/en/abs/design-and-implementation-of-an-improved-carry-increment-adder-1603.040942016-03-22 https://scifaro.com/en/abs/modified-micropipline-architecture-for-synthesizable-asynchronous-fir-filter-design-1603.046272016-03-16 https://scifaro.com/en/abs/asic-based-implementation-of-synchronous-section-carry-based-carry-lookahead-adders-1603.079612016-03-28 https://scifaro.com/en/abs/global-versus-local-weak-indication-self-timed-function-blocks-a-comparative-analysis-1603.079622016-03-28 https://scifaro.com/en/abs/power-delay-and-area-comparisons-of-majority-voters-relevant-to-tmr-architectures-1603.079642016-03-28 https://scifaro.com/en/abs/adaptive-latency-dram-al-dram-1603.084542016-03-29 https://scifaro.com/en/abs/fpga-impementation-of-erasure-only-reed-solomon-decoders-for-hybrid-arq-systems-1603.090622016-03-31 https://scifaro.com/en/abs/clear-cross-layer-exploration-for-architecting-resilience-combining-hardware-and-software-techniques-to-tolerate-soft-errors-in-processor-cores-1604.030622016-06-27 https://scifaro.com/en/abs/area-latency-optimized-early-output-asynchronous-full-adders-and-relative-timed-ripple-carry-adders-1604.040062016-04-15 https://scifaro.com/en/abs/reducing-dram-latency-at-low-cost-by-exploiting-heterogeneity-1604.080412016-11-01 https://scifaro.com/en/abs/cordic-based-architecture-for-powering-computation-in-fixed-point-arithmetic-1605.032292016-05-12 https://scifaro.com/en/abs/an-asynchronous-early-output-full-adder-and-a-relative-timed-ripple-carry-adder-1605.037702017-11-09 https://scifaro.com/en/abs/a-fault-tolerance-improved-majority-voter-for-tmr-system-architectures-1605.037712017-11-09 https://scifaro.com/en/abs/a-foray-into-efficient-mapping-of-algorithms-to-hardware-platforms-on-heterogeneous-systems-1605.045822016-05-24 https://scifaro.com/en/abs/simple-dram-and-virtual-memory-abstractions-to-enable-highly-efficient-memory-systems-1605.064832016-05-23 https://scifaro.com/en/abs/proceedings-of-the-2nd-international-workshop-on-overlay-architectures-for-fpgas-olaf-2016-1605.081492016-05-27 https://scifaro.com/en/abs/grvi-phalanx-a-massively-parallel-risc-v-fpga-accelerator-accelerator-1606.010372016-06-06 https://scifaro.com/en/abs/cg-ooo-energy-efficient-coarse-grain-out-of-order-execution-1606.016072016-06-07 https://scifaro.com/en/abs/open-source-hardware-opportunities-and-challenges-1606.019802016-06-14 https://scifaro.com/en/abs/mac-a-novel-systematically-multilevel-cache-replacement-policy-for-pcm-memory-1606.032482016-06-13 https://scifaro.com/en/abs/automated-space-time-scaling-of-streaming-task-graph-1606.037172016-06-14 https://scifaro.com/en/abs/entra-whole-systems-energy-transparency-1606.040742020-05-18 https://scifaro.com/en/abs/high-throughput-neural-network-based-embedded-streaming-multicore-processors-1606.046092016-06-16 https://scifaro.com/en/abs/a-0-3-2-6-tops-w-precision-scalable-processor-for-real-time-large-scale-convnets-1606.050942016-06-17 https://scifaro.com/en/abs/yodann-an-architecture-for-ultra-low-power-binary-weight-cnn-acceleration-1606.054872017-02-27 https://scifaro.com/en/abs/design-of-synchronous-section-carry-based-carry-lookahead-adders-with-improved-figure-of-merit-1606.056212017-11-09 https://scifaro.com/en/abs/criticality-aware-multiprocessors-1606.059332016-06-21 https://scifaro.com/en/abs/high-level-synthesis-with-a-dataflow-architectural-template-1606.064512016-06-22 https://scifaro.com/en/abs/reliability-aware-overlay-architectures-for-fpgas-features-and-design-challenges-1606.064522016-06-22 https://scifaro.com/en/abs/soft-gpgpus-for-embedded-fpgas-an-architectural-evaluation-1606.064542016-06-22 https://scifaro.com/en/abs/enabling-effective-fpga-debug-using-overlays-opportunities-and-challenges-1606.064572016-06-22 https://scifaro.com/en/abs/an-area-efficient-fpga-overlay-using-dsp-block-based-time-multiplexed-functional-units-1606.064602016-06-22 https://scifaro.com/en/abs/a-soft-processor-overlay-with-tightly-coupled-fpga-accelerator-1606.064832016-06-22 https://scifaro.com/en/abs/fpmax-a-106gflops-w-at-217gflops-mm2-single-precision-fpu-and-a-43-7gflops-w-at-74-6gflops-mm2-double-precision-fpu-in-28nm-utbb-fdsoi-1606.078522016-06-28 https://scifaro.com/en/abs/a-benes-based-noc-switching-architecture-for-mixed-criticality-embedded-systems-1606.086862016-06-29 https://scifaro.com/en/abs/maximizing-cnn-accelerator-efficiency-through-resource-partitioning-1607.000642018-04-13 https://scifaro.com/en/abs/reducing-the-energy-cost-of-inference-via-in-sensor-information-processing-1607.006672016-07-05 https://scifaro.com/en/abs/the-renewed-case-for-the-reduced-instruction-set-computer-avoiding-isa-bloat-with-macro-op-fusion-for-risc-v-1607.023182016-07-11 https://scifaro.com/en/abs/scratchpad-sharing-in-gpus-1607.032382017-02-14 https://scifaro.com/en/abs/uber-utilizing-buffers-to-simplify-nocs-for-hundreds-cores-1607.077662016-07-28 https://scifaro.com/en/abs/read-tuned-stt-ram-and-edram-cache-hierarchies-for-throughput-and-energy-enhancement-1607.080862016-08-09 https://scifaro.com/en/abs/the-study-of-transient-faults-propagation-in-multithread-applications-1607.085232016-07-29 https://scifaro.com/en/abs/early-output-hybrid-input-encoded-asynchronous-full-adder-and-relative-timed-ripple-carry-adder-1608.012252016-08-04 https://scifaro.com/en/abs/system-reliability-fault-tolerance-and-design-metrics-tradeoffs-in-the-distributed-minority-and-majority-voting-based-redundancy-scheme-1608.070362017-11-09 https://scifaro.com/en/abs/when-to-use-3d-die-stacked-memory-for-bandwidth-constrained-big-data-workloads-1608.074852016-08-29 https://scifaro.com/en/abs/tricheck-memory-model-verification-at-the-trisection-of-software-hardware-and-isa-1608.075472017-02-09 https://scifaro.com/en/abs/a-near-threshold-risc-v-core-with-dsp-extensions-for-scalable-iot-endpoint-devices-1608.083762016-08-31 https://scifaro.com/en/abs/on-chip-mechanisms-to-reduce-effective-memory-access-latency-1609.003062016-09-02 https://scifaro.com/en/abs/a-hardware-efficient-approach-to-computing-the-rotation-matrix-from-a-quaternion-1609.015852016-09-07 https://scifaro.com/en/abs/practical-data-compression-for-modern-memory-hierarchies-1609.020672016-09-08 https://scifaro.com/en/abs/design-of-a-ternary-edge-triggered-d-flip-flap-flop-for-multiple-valued-sequential-logic-1609.038972017-03-13 https://scifaro.com/en/abs/fpga-implementation-of-a-novel-image-steganography-for-hiding-images-1609.045692016-10-04 https://scifaro.com/en/abs/design-of-an-optoelectronic-state-machine-with-integrated-bdd-based-optical-logic-1609.049132016-09-19 https://scifaro.com/en/abs/reducing-dram-access-latency-by-exploiting-dram-leakage-characteristics-and-common-access-patterns-1609.072342016-09-26 https://scifaro.com/en/abs/multi-valued-routing-tracks-for-fpgas-in-28nm-fdsoi-technology-1609.086812016-09-29 https://scifaro.com/en/abs/an-overview-about-networks-on-chip-with-multicast-suppor-1610.007512016-10-05 https://scifaro.com/en/abs/epiphany-v-a-1024-processor-64-bit-risc-system-on-chip-1610.018322016-10-07 https://scifaro.com/en/abs/validating-simplified-processor-models-in-architectural-studies-1610.020942016-10-10 https://scifaro.com/en/abs/near-data-processing-for-differentiable-machine-learning-models-1610.022732017-05-01 https://scifaro.com/en/abs/a-9-52-db-ncg-fec-scheme-and-164-bits-cycle-low-complexity-product-decoder-architecture-1610.060502017-09-01 https://scifaro.com/en/abs/accelerating-blas-on-custom-architecture-through-algorithm-architecture-co-design-1610.063852016-11-29 https://scifaro.com/en/abs/a-481pj-decision-3-4m-decision-s-multifunctional-deep-in-memory-inference-processor-using-standard-6t-sram-array-1610.075012016-10-25 https://scifaro.com/en/abs/accelerating-blas-and-lapack-via-efficient-floating-point-architecture-design-1610.087052017-11-15 https://scifaro.com/en/abs/the-processing-using-memory-paradigm-in-dram-bulk-copy-initialization-bitwise-and-and-or-1610.096032016-11-01 https://scifaro.com/en/abs/understanding-and-exploiting-design-induced-latency-variation-in-modern-dram-chips-1610.096042017-05-17 https://scifaro.com/en/abs/araprototyper-enabling-rapid-prototyping-and-evaluation-for-accelerator-rich-architectures-1610.097612016-11-01 https://scifaro.com/en/abs/flat-oram-a-simplified-write-only-oblivious-ram-construction-for-secure-processors-1611.015712017-09-12 https://scifaro.com/en/abs/pipecnn-an-opencl-based-fpga-accelerator-for-large-scale-convolution-neuron-networks-1611.024502016-11-09 https://scifaro.com/en/abs/non-volatile-hierarchical-temporal-memory-hardware-for-spatial-pooling-1611.027922016-11-10 https://scifaro.com/en/abs/power-gating-structure-for-reversible-programmable-logic-array-1611.029152016-11-10 https://scifaro.com/en/abs/in-storage-embedded-accelerator-for-sparse-pattern-processing-1611.033802017-01-25 https://scifaro.com/en/abs/multipliers-comparison-of-fourier-transformation-based-method-and-synopsys-design-technique-for-up-to-32-bits-inputs-in-regular-and-saturation-arithmetics-1611.054152016-11-17 https://scifaro.com/en/abs/fast-and-reconfigurable-packet-classification-engine-in-fpga-based-firewall-1611.060782016-11-21 https://scifaro.com/en/abs/fpga-based-implementation-of-distributed-minority-and-majority-voting-based-redundancy-for-mission-and-safety-critical-applications-1611.094462016-11-30 https://scifaro.com/en/abs/an-efficient-partial-sums-generator-for-constituent-code-based-successive-cancellation-decoding-of-polar-codes-1611.094522017-03-08 https://scifaro.com/en/abs/buddy-ram-improving-the-performance-and-efficiency-of-bulk-bitwise-operations-using-dram-1611.099882016-12-01 https://scifaro.com/en/abs/memory-controller-design-under-cloud-workloads-1611.103162016-12-01 https://scifaro.com/en/abs/near-memory-address-translation-1612.004452017-08-23 https://scifaro.com/en/abs/arch2030-a-vision-of-computer-architecture-research-over-the-next-15-years-1612.031822016-12-13 https://scifaro.com/en/abs/copycat-a-high-precision-real-time-nand-simulator-1612.042772016-12-22 https://scifaro.com/en/abs/a-700uw-1gs-s-4-bit-folding-flash-adc-in-65nm-cmos-for-wideband-wireless-communications-1612.048552016-12-16 https://scifaro.com/en/abs/hades-microprocessor-hazard-analysis-via-formal-verification-of-parameterized-systems-1612.049862016-12-16 https://scifaro.com/en/abs/a-novel-rtl-atpg-model-based-on-gate-inherent-faults-gif-po-of-complex-gates-1612.051662016-12-16 https://scifaro.com/en/abs/prototyping-risc-based-reconfigurable-networking-applications-in-open-source-1612.055472016-12-19 https://scifaro.com/en/abs/an-iot-endpoint-system-on-chip-for-secure-and-energy-efficient-near-sensor-analytics-1612.059742017-11-27 https://scifaro.com/en/abs/application-aware-retiming-of-accelerators-a-high-level-data-driven-approach-1612.081632016-12-28 https://scifaro.com/en/abs/neutron-induced-strike-on-the-likelihood-of-multiple-bit-flips-in-logic-circuits-1612.082392017-06-16 https://scifaro.com/en/abs/reducing-competitive-cache-misses-in-modern-processor-architectures-1701.016302017-01-09 https://scifaro.com/en/abs/vespa-vipt-enhancements-for-superpage-accesses-1701.034992017-02-15 https://scifaro.com/en/abs/holiswap-reducing-wire-energy-in-l1-caches-1701.038782017-01-17 https://scifaro.com/en/abs/design-of-an-audio-interface-for-patmos-1701.063822017-01-24 https://scifaro.com/en/abs/neurostream-scalable-and-energy-efficient-deep-learning-with-smart-memory-cubes-1701.064202017-09-26 https://scifaro.com/en/abs/variability-aware-design-for-energy-efficient-computational-artificial-intelligence-platform-1701.067412017-02-16 https://scifaro.com/en/abs/hardware-translation-coherence-for-virtualized-systems-1701.075172017-02-16 https://scifaro.com/en/abs/accurate-measurement-of-power-consumption-overhead-during-fpga-dynamic-partial-reconfiguration-1701.088492017-02-01 https://scifaro.com/en/abs/1-5-bit-per-stage-8-bit-pipelined-cmos-a-d-converter-for-neuromophic-vision-processor-1701.088772017-02-16 https://scifaro.com/en/abs/fpga-based-real-time-105-channel-data-acquisition-platform-for-imaging-system-1702.004832017-02-09 https://scifaro.com/en/abs/a-multi-gbps-unrolled-hardware-list-decoder-for-a-systematic-polar-code-1702.009382017-05-10 https://scifaro.com/en/abs/sense-amplifier-comparator-with-offset-correction-for-decision-feedback-equalization-based-receivers-1702.010672017-02-06 https://scifaro.com/en/abs/embedded-systems-architecture-for-slam-applications-1702.012952017-02-07 https://scifaro.com/en/abs/caad-computer-architecture-for-autonomous-driving-1702.018942017-02-08 https://scifaro.com/en/abs/fashion-fault-aware-self-healing-intelligent-on-chip-network-1702.023132017-02-09 https://scifaro.com/en/abs/chain-nn-an-energy-efficient-1d-chain-architecture-for-accelerating-deep-convolutional-neural-networks-1703.014572017-03-07 https://scifaro.com/en/abs/a-588-gbps-ldpc-decoder-based-on-finite-alphabet-message-passing-1703.057692018-01-03 https://scifaro.com/en/abs/unbias-puf-a-physical-implementation-bias-agnostic-strong-puf-1703.107252017-04-03 https://scifaro.com/en/abs/banshee-bandwidth-efficient-dram-caching-via-software-hardware-cooperation-1704.026772017-04-11 https://scifaro.com/en/abs/fmmu-a-hardware-automated-flash-map-management-unit-for-scalable-performance-of-nand-flash-based-ssds-1704.031682017-04-12 https://scifaro.com/en/abs/architectural-techniques-to-enable-reliable-and-scalable-memory-systems-1704.039912019-09-04 https://scifaro.com/en/abs/in-datacenter-performance-analysis-of-a-tensor-processing-unit-1704.047602017-04-18 https://scifaro.com/en/abs/a-study-on-performance-and-power-efficiency-of-dense-non-volatile-caches-in-multi-core-systems-1704.050442017-06-13 https://scifaro.com/en/abs/exploiting-data-longevity-for-enhancing-the-lifetime-of-flash-based-storage-class-memory-1704.051382017-04-19 https://scifaro.com/en/abs/asynchronous-early-output-dual-bit-full-adders-based-on-homogeneous-and-heterogeneous-delay-insensitive-data-encoding-1704.076192017-04-26 https://scifaro.com/en/abs/an-efficient-reconfigurable-fir-digital-filter-using-modified-distribute-arithmetic-technique-1704.085262017-04-28 https://scifaro.com/en/abs/proceedings-of-the-3rd-international-workshop-on-overlay-architectures-for-fpgas-olaf-2017-1704.088022019-03-06 https://scifaro.com/en/abs/a-floating-point-division-unit-based-on-taylor-series-expansion-algorithm-and-iterative-logarithmic-multiplier-1705.002182017-05-02 https://scifaro.com/en/abs/pixie-a-heterogeneous-virtual-coarse-grained-reconfigurable-array-for-high-performance-image-processing-applications-1705.017382017-05-05 https://scifaro.com/en/abs/static-timing-model-extraction-for-combinational-circuits-1705.026102017-05-09 https://scifaro.com/en/abs/resource-aware-just-in-time-opencl-compiler-for-coarse-grained-fpga-overlays-1705.027302017-05-09 https://scifaro.com/en/abs/a-scalable-low-overhead-finite-state-machine-overlay-for-rapid-fpga-application-development-1705.027322017-05-09 https://scifaro.com/en/abs/out-of-order-dataflow-scheduling-for-fpga-overlays-1705.027342017-05-09 https://scifaro.com/en/abs/improving-the-performance-and-endurance-of-persistent-memory-with-loose-ordering-consistency-1705.036232017-05-11 https://scifaro.com/en/abs/sprinkler-maximizing-resource-utilization-in-many-chip-solid-state-disks-1705.046272017-05-15 https://scifaro.com/en/abs/on-hierarchical-statistical-static-timing-analysis-1705.049752017-05-16 https://scifaro.com/en/abs/timing-model-extraction-for-sequential-circuits-considering-process-variations-1705.049762017-05-16 https://scifaro.com/en/abs/fast-statistical-timing-analysis-for-circuits-with-post-silicon-tunable-clock-buffers-1705.049792017-05-16 https://scifaro.com/en/abs/on-timing-model-extraction-and-hierarchical-statistical-timing-analysis-1705.049812017-05-16 https://scifaro.com/en/abs/post-route-refinement-for-high-frequency-pcbs-considering-meander-segment-alleviation-1705.049822017-05-16 https://scifaro.com/en/abs/post-route-alleviation-of-dense-meander-segments-in-high-performance-printed-circuit-boards-1705.049832017-05-16 https://scifaro.com/en/abs/ilp-based-alleviation-of-dense-meander-segments-with-prioritized-shifting-and-progressive-fixing-in-pcb-routing-1705.049842017-05-16 https://scifaro.com/en/abs/statistical-timing-analysis-and-criticality-computation-for-circuits-with-post-silicon-clock-tuning-elements-1705.049862017-05-16 https://scifaro.com/en/abs/sampling-based-buffer-insertion-for-post-silicon-yield-improvement-under-process-variability-1705.049902017-05-16 https://scifaro.com/en/abs/effitest-efficient-delay-test-and-statistical-prediction-for-configuring-post-silicon-tunable-buffers-1705.049922017-05-16 https://scifaro.com/en/abs/piecetimer-a-holistic-timing-analysis-framework-considering-setup-hold-time-interdependency-using-a-piecewise-model-1705.049932017-05-16 https://scifaro.com/en/abs/design-phase-buffer-allocation-for-post-silicon-clock-binning-by-iterative-learning-1705.049952017-05-16 https://scifaro.com/en/abs/simplessd-modeling-solid-state-drives-for-holistic-system-simulation-1705.064192017-09-15 https://scifaro.com/en/abs/multiamdahl-optimal-resource-allocation-in-heterogeneous-architectures-1705.069232017-05-22 https://scifaro.com/en/abs/the-effect-of-temperature-on-amdahl-law-in-3d-multicore-era-1705.072802017-05-23 https://scifaro.com/en/abs/cache-hierarchy-optimization-1705.072812017-05-23 https://scifaro.com/en/abs/some-schemes-for-implementation-of-arithmetic-operations-with-complex-numbers-using-squaring-units-1705.074652017-05-23 https://scifaro.com/en/abs/a-low-power-accelerator-for-deep-neural-networks-with-enlarged-near-zero-sparsity-1705.080092017-05-24 https://scifaro.com/en/abs/sparse-matrix-multiplication-on-cam-based-accelerator-1705.099372017-05-30 https://scifaro.com/en/abs/understanding-reduced-voltage-operation-in-modern-dram-chips-characterization-analysis-and-mechanisms-1705.102922017-05-30 https://scifaro.com/en/abs/energy-efficient-hybrid-stochastic-binary-neural-networks-for-near-sensor-computing-1706.023442017-06-09 https://scifaro.com/en/abs/demystifying-the-characteristics-of-3d-stacked-memories-a-case-study-for-hybrid-memory-cube-1706.027252018-12-05 https://scifaro.com/en/abs/lazypim-efficient-support-for-cache-coherence-in-processing-in-memory-architectures-1706.031622017-06-13 https://scifaro.com/en/abs/proposal-for-a-high-precision-tensor-processing-unit-1706.032512017-06-13 https://scifaro.com/en/abs/exploring-computation-communication-tradeoffs-in-camera-systems-1706.038642017-10-18 https://scifaro.com/en/abs/latency-optimized-asynchronous-early-output-ripple-carry-adder-based-on-delay-insensitive-dual-rail-data-encoding-1706.044872017-06-15 https://scifaro.com/en/abs/hourglass-predictable-time-based-cache-coherence-protocol-for-dual-critical-multi-core-systems-1706.075682018-07-20 https://scifaro.com/en/abs/error-characterization-mitigation-and-recovery-in-flash-memory-based-solid-state-drives-1706.086422017-09-25 https://scifaro.com/en/abs/using-ecc-dram-to-adaptively-increase-memory-capacity-1706.088702017-06-29 https://scifaro.com/en/abs/fast-processing-of-large-graph-applications-using-asynchronous-architecture-1706.099532017-07-03 https://scifaro.com/en/abs/pipelined-parallel-fft-architecture-1707.016972017-07-07 https://scifaro.com/en/abs/variable-instruction-fetch-rate-to-reduce-control-dependent-penalties-1707.046572017-07-18 https://scifaro.com/en/abs/deterministic-memory-abstraction-and-supporting-multicore-system-architecture-1707.052602018-04-20 https://scifaro.com/en/abs/performance-implications-of-nocs-on-3d-stacked-memories-insights-from-the-hybrid-memory-cube-1707.053992018-12-05 https://scifaro.com/en/abs/real-time-impulse-noise-removal-from-mr-images-for-radiosurgery-applications-1707.059752017-07-20 https://scifaro.com/en/abs/redundant-logic-insertion-and-fault-tolerance-improvement-in-combinational-circuits-1707.069092017-07-24 https://scifaro.com/en/abs/mathematical-estimation-of-logical-masking-capability-of-majority-minority-gates-used-in-nanoelectronic-circuits-1707.069132017-07-24 https://scifaro.com/en/abs/optimizing-scrubbing-by-netlist-analysis-for-fpga-configuration-bit-classification-and-floorplanning-1707.081342017-07-27 https://scifaro.com/en/abs/address-translation-design-tradeoffs-for-heterogeneous-systems-1707.094502017-08-01 https://scifaro.com/en/abs/multiscale-co-design-analysis-of-energy-latency-area-and-accuracy-of-a-reram-analog-neural-training-accelerator-1707.099522018-02-20 https://scifaro.com/en/abs/snowflake-a-model-agnostic-accelerator-for-deep-convolutional-neural-networks-1708.025792017-08-09 https://scifaro.com/en/abs/sensitivity-analysis-of-core-specialization-techniques-1708.039002017-08-15 https://scifaro.com/en/abs/a-scalable-multi-core-architecture-with-heterogeneous-memory-structures-for-dynamic-neuromorphic-asynchronous-processors-dynaps-1708.041982017-11-07 https://scifaro.com/en/abs/improving-multi-application-concurrency-support-within-the-gpu-memory-system-1708.049112017-08-17 https://scifaro.com/en/abs/advanced-datapath-synthesis-using-graph-isomorphism-1708.095972017-09-01 https://scifaro.com/en/abs/polarbear-a-28-nm-fd-soi-asic-for-decoding-of-polar-codes-1708.096032017-09-05 https://scifaro.com/en/abs/greener-a-tool-for-improving-energy-efficiency-of-register-files-1709.046972018-03-30 https://scifaro.com/en/abs/a-streaming-accelerator-for-deep-convolutional-neural-networks-with-image-and-feature-decomposition-for-resource-limited-system-applications-1709.051162017-09-18 https://scifaro.com/en/abs/satisfiability-modulo-theory-based-methodology-for-floorplanning-in-vlsi-circuits-1709.072412017-09-22 https://scifaro.com/en/abs/energy-efficient-wireless-interconnection-framework-for-multichip-systems-with-in-package-memory-stacks-1709.075292017-09-25 https://scifaro.com/en/abs/tolerating-soft-errors-in-processor-cores-using-clear-cross-layer-exploration-for-architecting-resilience-1709.099212017-09-29 https://scifaro.com/en/abs/neurotrainer-an-intelligent-memory-module-for-deep-learning-training-1710.043472017-10-13 https://scifaro.com/en/abs/high-throughput-2d-spatial-image-filters-on-fpgas-1710.051542017-10-18 https://scifaro.com/en/abs/asynchronous-early-output-section-carry-based-carry-lookahead-adder-with-alias-carry-logic-1710.054702017-10-17 https://scifaro.com/en/abs/approximate-ripple-carry-and-carry-lookahead-adders-a-comparative-analysis-1710.054742017-10-17 https://scifaro.com/en/abs/amorphous-dynamic-partial-reconfiguration-with-flexible-boundaries-to-remove-fragmentation-1710.082702017-10-26 https://scifaro.com/en/abs/coda-enabling-co-location-of-computation-and-data-for-near-data-processing-1710.095172018-12-05 https://scifaro.com/en/abs/a-single-channel-architecture-for-algebraic-integer-based-8-times-8-2-d-dct-computation-1710.099752017-10-30 https://scifaro.com/en/abs/using-vivado-hls-for-structural-design-a-noc-case-study-1710.102902020-08-18 https://scifaro.com/en/abs/louvre-lightweight-ordering-using-versioning-for-release-consistency-1710.107462017-12-07 https://scifaro.com/en/abs/vlsi-computational-architectures-for-the-arithmetic-cosine-transform-1710.112002017-11-01 https://scifaro.com/en/abs/non-uniform-on-chip-power-delivery-network-synthesis-methodology-1711.004252017-11-08 https://scifaro.com/en/abs/timing-aware-dummy-metal-fill-methodology-1711.014072017-11-08 https://scifaro.com/en/abs/critique-of-asynchronous-logic-implementation-based-on-factorized-dims-1711.023332018-09-25 https://scifaro.com/en/abs/a-dwarf-based-scalable-big-data-benchmarking-methodology-1711.032292017-11-10 https://scifaro.com/en/abs/depth-first-always-on-routing-trace-algorithm-1711.041722017-11-15 https://scifaro.com/en/abs/p4-compatible-high-level-synthesis-of-low-latency-100-gb-s-streaming-packet-parsers-in-fpgas-1711.066132018-03-22 https://scifaro.com/en/abs/decanting-the-contribution-of-instruction-types-and-loop-structures-in-the-reuse-of-traces-1711.066722017-11-20 https://scifaro.com/en/abs/mitigating-read-disturbance-errors-in-stt-ram-caches-by-using-data-compression-1711.067902017-11-21 https://scifaro.com/en/abs/bilbo-friendly-hybrid-bist-architecture-with-asymmetric-polynomial-reseeding-1711.084582017-11-27 https://scifaro.com/en/abs/enabling-fine-grain-restricted-coset-coding-through-word-level-compression-for-pcm-1711.085722017-11-27 https://scifaro.com/en/abs/a-transprecision-floating-point-platform-for-ultra-low-power-computing-1711.103742017-11-29 https://scifaro.com/en/abs/lp-based-power-grid-enhancement-methodology-1711.104352017-11-29 https://scifaro.com/en/abs/energy-efficient-time-domain-vector-by-matrix-multiplier-for-neurocomputing-and-beyond-1711.106732017-11-30 https://scifaro.com/en/abs/errors-in-flash-memory-based-solid-state-drives-analysis-mitigation-and-recovery-1711.114272018-01-08 https://scifaro.com/en/abs/data-cache-prefetching-with-perceptron-learning-1712.009052017-12-05 https://scifaro.com/en/abs/an-826-mops-210-uw-mhz-unum-alu-in-65-nm-1712.010212017-12-06 https://scifaro.com/en/abs/fpga-with-improved-routability-and-robustness-in-130nm-cmos-with-open-source-cad-targetability-1712.034112017-12-12 https://scifaro.com/en/abs/a-flexible-high-bandwidth-low-latency-multi-port-memory-controller-1712.034772018-06-12 https://scifaro.com/en/abs/a-scalable-high-performance-priority-encoder-using-1d-array-to-2d-array-conversion-1712.034782017-12-12 https://scifaro.com/en/abs/cross-layer-optimization-for-power-efficient-and-robust-digital-circuits-and-systems-1712.039482017-12-12 https://scifaro.com/en/abs/multi-mode-inference-engine-for-convolutional-neural-networks-1712.039942017-12-13 https://scifaro.com/en/abs/applying-the-residue-number-system-to-network-inference-1712.046142017-12-14 https://scifaro.com/en/abs/reconfigurable-hardware-accelerators-opportunities-trends-and-challenges-1712.047712017-12-14 https://scifaro.com/en/abs/accelerator-codesign-as-non-linear-optimization-1712.048922017-12-26 https://scifaro.com/en/abs/the-microarchitecture-of-a-multi-threaded-risc-v-compliant-processing-core-family-for-iot-end-nodes-1712.049022020-07-20 https://scifaro.com/en/abs/automated-flow-for-compressing-convolution-neural-networks-for-efficient-edge-computation-with-fpga-1712.062722017-12-19 https://scifaro.com/en/abs/hero-heterogeneous-embedded-research-platform-for-exploring-risc-v-manycore-accelerators-on-fpga-1712.064972017-12-19 https://scifaro.com/en/abs/improving-dram-performance-by-parallelizing-refreshes-with-accesses-1712.077542017-12-22 https://scifaro.com/en/abs/understanding-and-improving-the-latency-of-dram-based-memory-systems-1712.083042017-12-25 https://scifaro.com/en/abs/a-survey-of-fpga-based-neural-network-accelerator-1712.089342018-12-07 https://scifaro.com/en/abs/automated-formal-equivalence-verification-of-pipelined-nested-loops-in-datapath-designs-1712.098182017-12-29 https://scifaro.com/en/abs/auto-generation-of-pipelined-hardware-designs-for-polar-encoder-1801.004722018-01-03 https://scifaro.com/en/abs/instruction-level-abstraction-ila-a-uniform-specification-for-system-on-chip-soc-verification-1801.011142019-01-29 https://scifaro.com/en/abs/a-software-defined-soc-memory-bus-bridge-architecture-for-disaggregated-computing-1801.037122018-01-12 https://scifaro.com/en/abs/inter-thread-communication-in-multithreaded-reconfigurable-coarse-grain-arrays-1801.051782018-01-17 https://scifaro.com/en/abs/trends-in-processor-architecture-1801.052152022-03-14 https://scifaro.com/en/abs/approximate-early-output-asynchronous-adders-based-on-dual-rail-data-encoding-and-4-phase-return-to-zero-and-return-to-one-handshaking-1801.060702018-01-19 https://scifaro.com/en/abs/design-guidelines-for-high-performance-scm-hierarchies-1801.067262019-03-11 https://scifaro.com/en/abs/pointer-chase-prefetcher-for-linked-data-structures-1801.080882018-01-25 https://scifaro.com/en/abs/low-complexity-multiply-accumulate-units-for-convolutional-neural-networks-with-weight-sharing-1801.102192018-05-03 https://scifaro.com/en/abs/enabling-the-adoption-of-processing-in-memory-challenges-mechanisms-future-research-directions-1802.003202018-02-02 https://scifaro.com/en/abs/a-multi-kernel-multi-code-polar-decoder-architecture-1802.005802018-02-05 https://scifaro.com/en/abs/polar-coded-forward-error-correction-for-mlc-nand-flash-memory-polar-fec-for-nand-flash-memory-1802.045762018-02-14 https://scifaro.com/en/abs/sapa-self-aware-polymorphic-architecture-1802.051002018-02-15 https://scifaro.com/en/abs/high-speed-srt-divider-for-intelligent-embedded-system-1802.061952018-02-20 https://scifaro.com/en/abs/45-year-cpu-evolution-one-law-and-two-equations-1803.002542018-03-02 https://scifaro.com/en/abs/adaptive-3d-ic-tsv-fault-tolerance-structure-generation-1803.024902018-03-08 https://scifaro.com/en/abs/synthesizing-power-and-area-efficient-image-processing-pipelines-on-fpgas-using-customized-bit-widths-1803.026602018-12-20 https://scifaro.com/en/abs/efficient-reconfigurable-regions-management-method-for-adaptive-and-dynamic-fpga-based-systems-1803.033312018-03-12 https://scifaro.com/en/abs/integrated-optimization-of-partitioning-scheduling-and-floorplanning-for-partially-dynamically-reconfigurable-systems-1803.037482018-12-27 https://scifaro.com/en/abs/towards-a-multi-array-architecture-for-accelerating-large-scale-matrix-multiplication-on-fpgas-1803.037902018-03-13 https://scifaro.com/en/abs/memory-slices-a-modular-building-block-for-scalable-intelligent-memory-systems-1803.060682018-03-19 https://scifaro.com/en/abs/the-arm-scalable-vector-extension-1803.061852018-03-19 https://scifaro.com/en/abs/towards-an-area-efficient-implementation-of-a-high-ilp-edge-soft-processor-1803.066172018-03-20 https://scifaro.com/en/abs/aisc-approximate-instruction-set-computer-1803.069552018-03-20 https://scifaro.com/en/abs/techniques-for-shared-resource-management-in-systems-with-throughput-processors-1803.069582018-05-01 https://scifaro.com/en/abs/integrating-dram-power-down-modes-in-gem5-and-quantifying-their-impact-1803.076132018-03-22 https://scifaro.com/en/abs/an-fpga-based-hardware-accelerator-for-energy-efficient-bitmap-index-creation-1803.112072018-04-24 https://scifaro.com/en/abs/a-survey-of-techniques-for-dynamic-branch-prediction-1804.002612018-04-03 https://scifaro.com/en/abs/an-efficient-i-o-architecture-for-ram-based-content-addressable-memory-on-fpga-1804.023302018-06-28 https://scifaro.com/en/abs/holistic-management-of-the-gpgpu-memory-hierarchy-to-manage-warp-level-latency-tolerance-1804.110382018-05-01 https://scifaro.com/en/abs/a-memory-controller-with-row-buffer-locality-awareness-for-hybrid-memory-systems-1804.110402018-05-01 https://scifaro.com/en/abs/high-performance-and-energy-effcient-memory-scheduler-design-for-heterogeneous-systems-1804.110432018-05-01 https://scifaro.com/en/abs/dynamically-improving-branch-prediction-accuracy-between-contexts-1805.005852018-05-03 https://scifaro.com/en/abs/eci-cache-a-high-endurance-and-cost-efficient-i-o-caching-scheme-for-virtualized-platforms-1805.009762018-05-04 https://scifaro.com/en/abs/reducing-dram-refresh-overheads-with-refresh-access-parallelism-1805.012892018-05-04 https://scifaro.com/en/abs/exploiting-the-dram-microarchitecture-to-increase-memory-level-parallelism-1805.019662018-05-08 https://scifaro.com/en/abs/flashabacus-a-self-governing-flash-based-accelerator-for-low-power-systems-1805.028072018-05-09 https://scifaro.com/en/abs/experimental-characterization-optimization-and-recovery-of-data-retention-errors-in-mlc-nand-flash-memory-1805.028192018-05-09 https://scifaro.com/en/abs/hierarchical-temporal-memory-using-memristor-networks-a-survey-1805.029212018-05-09 https://scifaro.com/en/abs/adaptive-latency-dram-reducing-dram-latency-by-exploiting-timing-margins-1805.030472018-05-09 https://scifaro.com/en/abs/tiered-latency-dram-enabling-low-latency-main-memory-at-low-cost-1805.030482018-05-09 https://scifaro.com/en/abs/flexible-latency-dram-understanding-and-exploiting-latency-variation-in-modern-dram-chips-1805.031542018-05-09 https://scifaro.com/en/abs/voltron-understanding-and-exploiting-the-voltage-latency-reliability-trade-offs-in-modern-dram-chips-to-improve-energy-efficiency-1805.031752018-05-09 https://scifaro.com/en/abs/lisa-increasing-internal-connectivity-in-dram-for-fast-data-movement-and-low-latency-1805.031842018-05-09 https://scifaro.com/en/abs/softmc-practical-dram-characterization-using-an-fpga-based-infrastructure-1805.031952018-05-09 https://scifaro.com/en/abs/read-disturb-errors-in-mlc-nand-flash-memory-1805.032832018-05-10 https://scifaro.com/en/abs/characterizing-exploiting-and-mitigating-vulnerabilities-in-mlc-nand-flash-memory-programming-1805.032912018-05-10 https://scifaro.com/en/abs/rowclone-accelerating-data-movement-and-initialization-using-dram-1805.035022018-05-10 https://scifaro.com/en/abs/parallel-programming-for-fpgas-1805.036482018-05-11 https://scifaro.com/en/abs/neural-cache-bit-serial-in-cache-acceleration-of-deep-neural-networks-1805.037182018-05-11 https://scifaro.com/en/abs/exploiting-row-level-temporal-locality-in-dram-to-reduce-the-memory-access-latency-1805.039692018-05-11 https://scifaro.com/en/abs/predictable-performance-and-fairness-through-accurate-slowdown-estimation-in-shared-main-memory-systems-1805.059262018-05-16 https://scifaro.com/en/abs/blasys-approximate-logic-synthesis-using-boolean-matrix-factorization-1805.060502018-05-17 https://scifaro.com/en/abs/recent-advances-in-overcoming-bottlenecks-in-memory-systems-and-managing-memory-resources-in-gpu-systems-1805.064072018-05-30 https://scifaro.com/en/abs/lector-based-clock-gating-for-low-power-multi-stage-flip-flop-applications-1805.074092018-05-22 https://scifaro.com/en/abs/ciao-cache-interference-aware-throughput-oriented-architecture-and-scheduling-for-gpus-1805.077182018-05-22 https://scifaro.com/en/abs/constructing-a-weak-memory-model-1805.078862018-09-20 https://scifaro.com/en/abs/recent-advances-in-dram-and-flash-memory-architectures-1805.091272018-05-31 https://scifaro.com/en/abs/prins-resistive-cam-processing-in-storage-1805.096122019-03-19 https://scifaro.com/en/abs/time-shared-execution-of-realtime-computer-vision-pipelines-by-dynamic-partial-reconfiguration-1805.104312018-06-22 https://scifaro.com/en/abs/lake-an-energy-efficient-low-latency-accelerated-key-value-store-1805.113442018-05-30 https://scifaro.com/en/abs/supporting-superpages-and-lightweight-page-migration-in-hybrid-memory-systems-1806.007762018-06-05 https://scifaro.com/en/abs/gemini-reducing-dram-cache-hit-latency-by-hybrid-mappings-1806.007792018-06-05 https://scifaro.com/en/abs/data-dependent-clock-gating-approach-for-low-power-sequential-system-1806.022712018-06-07 https://scifaro.com/en/abs/mitigating-wordline-crosstalk-using-adaptive-trees-of-counters-1806.024982018-06-08 https://scifaro.com/en/abs/a-1-2-v-162-9-pj-cycle-bitmap-index-creation-core-with-0-31-pw-bit-standby-power-on-65-nm-sotb-1806.069022018-06-20 https://scifaro.com/en/abs/generic-and-universal-parallel-matrix-summation-with-a-flexible-compression-goal-for-xilinx-fpgas-1806.080952018-06-22 https://scifaro.com/en/abs/bismo-a-scalable-bit-serial-matrix-multiplication-overlay-for-reconfigurable-computing-1806.088622018-06-26 https://scifaro.com/en/abs/best-effort-fpga-programming-a-few-steps-can-go-a-long-way-1807.013402018-07-05 https://scifaro.com/en/abs/crosstalk-based-fine-grained-reconfiguration-techniques-for-polymorphic-circuits-1807.014312018-07-05 https://scifaro.com/en/abs/a-new-paradigm-for-fault-tolerant-computing-with-interconnect-crosstalks-1807.014332018-07-08 https://scifaro.com/en/abs/medusa-a-scalable-interconnect-for-many-port-dnn-accelerators-and-wide-dram-controller-interfaces-1807.040132018-07-12 https://scifaro.com/en/abs/what-your-dram-power-models-are-not-telling-you-lessons-from-a-detailed-experimental-study-1807.051022018-07-16 https://scifaro.com/en/abs/improving-3d-nand-flash-memory-lifetime-by-tolerating-early-retention-loss-and-process-variation-1807.051402018-11-13 https://scifaro.com/en/abs/deriving-aoc-c-models-from-d-v-languages-for-single-or-multi-threaded-execution-using-c-or-c-1807.054422018-07-17 https://scifaro.com/en/abs/timing-driven-c-slow-retiming-on-rtl-for-multicores-on-fpgas-1807.054462018-07-17 https://scifaro.com/en/abs/cross-layer-optimization-for-high-speed-adders-a-pareto-driven-machine-learning-approach-1807.070232018-10-17 https://scifaro.com/en/abs/cram-efficient-hardware-based-memory-compression-for-bandwidth-enhancement-1807.076852018-07-23 https://scifaro.com/en/abs/rendering-elimination-early-discard-of-redundant-tiles-in-the-graphics-pipeline-1807.094492018-07-26 https://scifaro.com/en/abs/asynchronous-ripple-carry-adder-based-on-area-optimized-early-output-dual-bit-full-adder-1807.097622018-07-27 https://scifaro.com/en/abs/standard-cell-library-design-and-optimization-methodology-for-asap7-pdk-1807.113962018-07-31 https://scifaro.com/en/abs/the-basejump-manycore-accelerator-network-1808.006502018-08-16 https://scifaro.com/en/abs/energy-efficiency-prediction-of-multithreaded-workloads-on-heterogeneous-composite-cores-architectures-using-machine-learning-techniques-1808.017282018-08-07 https://scifaro.com/en/abs/eqasm-an-executable-quantum-instruction-set-architecture-1808.024492019-03-12 https://scifaro.com/en/abs/hardware-realization-of-residue-number-system-algorithms-by-boolean-functions-minimization-1808.030832018-08-10 https://scifaro.com/en/abs/architectural-techniques-for-improving-nand-flash-memory-reliability-1808.040162018-08-16 https://scifaro.com/en/abs/d-range-using-commodity-dram-devices-to-generate-true-random-numbers-with-low-latency-and-high-throughput-1808.042862018-12-27 https://scifaro.com/en/abs/scale-out-processors-energy-efficiency-1808.048642018-08-16 https://scifaro.com/en/abs/making-belady-inspired-replacement-policies-more-effective-using-expected-hit-count-1808.050242018-08-16 https://scifaro.com/en/abs/wrangling-rogues-managing-experimental-post-moore-architectures-1808.063342019-08-05 https://scifaro.com/en/abs/trinity-coordinated-performance-energy-and-temperature-management-in-3d-processor-memory-stacks-1808.090872018-09-11 https://scifaro.com/en/abs/implications-of-integrated-cpu-gpu-processors-on-thermal-and-power-management-techniques-1808.096512018-08-30 https://scifaro.com/en/abs/scalable-and-efficient-virtual-memory-sharing-in-heterogeneous-socs-with-tlb-prefetching-and-mmu-aware-dma-engine-1808.097512018-08-30 https://scifaro.com/en/abs/accelerating-viterbi-algorithm-using-custom-instruction-approach-1809.028872018-09-11 https://scifaro.com/en/abs/is-leakage-power-a-linear-function-of-temperature-1809.031472018-09-11 https://scifaro.com/en/abs/finn-r-an-end-to-end-deep-learning-framework-for-fast-exploration-of-quantized-neural-networks-1809.045702018-09-13 https://scifaro.com/en/abs/exploiting-errors-for-efficiency-a-survey-from-circuits-to-algorithms-1809.058592018-09-18 https://scifaro.com/en/abs/the-impact-of-on-chip-communication-on-memory-technologies-for-neuromorphic-systems-1809.060162018-11-14 https://scifaro.com/en/abs/in-memory-multiplication-engine-with-sot-mram-based-stochastic-computing-1809.083582018-09-25 https://scifaro.com/en/abs/die-stacked-dram-memory-cache-or-memcache-1809.088282018-09-25 https://scifaro.com/en/abs/improving-reliability-security-and-efficiency-of-reconfigurable-hardware-systems-1809.111562018-10-01 https://scifaro.com/en/abs/performance-comparison-of-some-synchronous-adders-1810.011152018-10-03 https://scifaro.com/en/abs/memory-vulnerability-a-case-for-delaying-error-reporting-1810.064722023-08-02 https://scifaro.com/en/abs/an-area-efficient-2d-fourier-transform-architecture-for-fpga-implementation-1810.068852018-10-17 https://scifaro.com/en/abs/on-the-off-chip-memory-latency-of-real-time-systems-is-ddr-dram-really-the-best-option-1810.070592018-10-17 https://scifaro.com/en/abs/exploring-modern-gpu-memory-system-design-challenges-through-accurate-modeling-1810.072692020-06-04 https://scifaro.com/en/abs/criticality-aware-soft-error-mitigation-in-the-configuration-memory-of-sram-based-fpga-1810.096612018-10-24 https://scifaro.com/en/abs/architectural-exploration-of-heterogeneous-memory-systems-1810.125732018-10-31 https://scifaro.com/en/abs/amber-enabling-precise-full-system-simulation-with-detailed-modeling-of-all-ssd-resources-1811.015442018-11-06 https://scifaro.com/en/abs/top-down-transaction-level-design-with-tl-verilog-1811.017802018-11-06 https://scifaro.com/en/abs/a-microprocessor-implemented-in-65nm-cmos-with-configurable-and-bit-scalable-accelerator-for-programmable-in-memory-computing-1811.040472020-09-17 https://scifaro.com/en/abs/architectural-space-exploration-of-heterogeneous-reliability-and-checkpointing-modes-for-out-of-order-superscalar-processors-1811.076122019-10-22 https://scifaro.com/en/abs/juxtapiton-enabling-heterogeneous-isa-research-with-risc-v-and-sparc-fpga-soft-cores-1811.080912018-11-21 https://scifaro.com/en/abs/building-the-case-for-temperature-awareness-in-energy-consumption-models-an-application-of-the-energy-frequency-convexity-rule-1811.092852019-05-06 https://scifaro.com/en/abs/formally-verifying-warp-v-an-open-source-tl-verilog-risc-v-core-generator-1811.124742018-12-03 https://scifaro.com/en/abs/repairability-enhancement-of-scalable-systems-with-locally-shared-spares-1812.012092018-12-05 https://scifaro.com/en/abs/r3-dla-reduce-reuse-recycle-a-more-efficient-approach-to-decoupled-look-ahead-architectures-1812.045142018-12-14 https://scifaro.com/en/abs/evaluating-row-buffer-locality-in-future-non-volatile-main-memories-1812.063772018-12-18 https://scifaro.com/en/abs/rapid-cycle-accurate-simulator-for-high-level-synthesis-1812.070122018-12-27 https://scifaro.com/en/abs/computational-ram-to-accelerate-string-matching-at-scale-1812.089182018-12-24 https://scifaro.com/en/abs/a-complexity-reduction-method-for-successive-cancellation-list-decoding-1812.093572019-08-20 https://scifaro.com/en/abs/a-256kb-9t-near-threshold-sram-with-1k-cells-per-bit-line-and-enhanced-write-and-read-operations-1812.100112019-01-07 https://scifaro.com/en/abs/high-performance-gnr-power-gating-for-low-voltage-cmos-circuits-1901.000922019-01-03 https://scifaro.com/en/abs/optimizing-bit-serial-matrix-multiplication-for-reconfigurable-computing-1901.003702019-06-12 https://scifaro.com/en/abs/asynchronous-early-output-block-carry-lookahead-adder-with-improved-quality-of-results-1901.093152019-01-29 https://scifaro.com/en/abs/majority-and-minority-voted-redundancy-for-safety-critical-applications-1901.093162019-01-29 https://scifaro.com/en/abs/eva-cim-a-system-level-performance-and-energy-evaluation-framework-for-computing-in-memory-architectures-1901.093482020-01-16 https://scifaro.com/en/abs/generic-connectivity-based-cgra-mapping-via-integer-linear-programming-1901.111292019-05-02 https://scifaro.com/en/abs/approximate-logic-synthesis-a-reinforcement-learning-based-technology-mapping-approach-1902.004782019-02-04 https://scifaro.com/en/abs/hybrid-cell-assignment-and-sizing-for-power-area-delay-product-optimization-of-sram-arrays-1902.004842019-02-04 https://scifaro.com/en/abs/routing-in-networks-on-chip-with-multiplicative-circulant-topology-1902.033142019-03-29 https://scifaro.com/en/abs/a-case-for-superconducting-accelerators-1902.046412019-02-15 https://scifaro.com/en/abs/fast-parallel-integer-adder-in-binary-representation-1902.050672019-03-26 https://scifaro.com/en/abs/enbb-processor-towards-the-exascale-numerical-brain-box-position-paper-1902.066552019-02-19 https://scifaro.com/en/abs/applicability-of-partial-ternary-full-adder-in-ternary-arithmetic-units-1902.067422019-02-20 https://scifaro.com/en/abs/understanding-the-interactions-of-workloads-and-dram-types-a-comprehensive-experimental-study-1902.076092019-10-21 https://scifaro.com/en/abs/ersfq-8-bit-parallel-binary-shifter-for-energy-efficient-superconducting-cpu-1902.078362019-05-01 https://scifaro.com/en/abs/ersfq-8-bit-parallel-arithmetic-logic-unit-1902.095002019-05-01 https://scifaro.com/en/abs/mips-core-application-specific-instruction-set-processor-for-idea-cryptography-comparison-between-single-cycle-and-multi-cycle-architectures-1903.001912019-03-04 https://scifaro.com/en/abs/denial-of-service-attacks-on-shared-cache-in-multicore-analysis-and-prevention-1903.013142019-03-05 https://scifaro.com/en/abs/fuse-fusing-stt-mram-into-gpus-to-alleviate-off-chip-memory-access-overheads-1903.017762019-03-12 https://scifaro.com/en/abs/buddy-compression-enabling-larger-memory-for-deep-learning-and-hpc-workloads-on-gpus-1903.025962019-04-17 https://scifaro.com/en/abs/processing-data-where-it-makes-sense-enabling-in-memory-computation-1903.039882019-03-12 https://scifaro.com/en/abs/automated-circuit-approximation-method-driven-by-data-distribution-1903.041882019-07-30 https://scifaro.com/en/abs/evaluating-modern-gpu-interconnect-pcie-nvlink-nv-sli-nvswitch-and-gpudirect-1903.046112019-08-26 https://scifaro.com/en/abs/a-68-uw-31-ks-s-fully-capacitive-noise-shaping-sar-adc-with-102-db-sndr-1903.086802019-03-22 https://scifaro.com/en/abs/fault-tolerant-nanosatellite-computing-on-a-budget-1903.087812019-03-22 https://scifaro.com/en/abs/speed-and-energy-optimised-quasi-delay-insensitive-block-carry-lookahead-adder-1903.094332019-03-25 https://scifaro.com/en/abs/an-analytical-model-for-performance-and-lifetime-estimation-of-hybrid-dram-nvm-main-memories-1903.100672019-03-26 https://scifaro.com/en/abs/a-novel-hierarchical-circuit-lut-model-for-soi-technology-for-rapid-prototyping-1903.112642019-04-29 https://scifaro.com/en/abs/evaluating-built-in-ecc-of-fpga-on-chip-memories-for-the-mitigation-of-undervolting-faults-1903.125142019-04-01 https://scifaro.com/en/abs/ring-mesh-a-scalable-and-high-performance-approach-for-manycore-accelerators-1904.034282019-12-16 https://scifaro.com/en/abs/higher-level-hardware-synthesis-of-the-kasumi-algorithm-1904.037562019-04-09 https://scifaro.com/en/abs/high-performance-reconfigurable-computing-systems-1904.049532019-04-11 https://scifaro.com/en/abs/an-application-specific-vliw-processor-with-vector-instruction-set-for-cnn-acceleration-1904.051062019-07-18 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https://scifaro.com/en/abs/low-power-programmable-processor-for-fast-fourier-transform-based-on-transport-triggered-architecture-1905.082392019-05-22 https://scifaro.com/en/abs/performance-analysis-of-6t-and-9t-sram-1905.086242019-05-22 https://scifaro.com/en/abs/in-dram-bulk-bitwise-execution-engine-1905.098222020-04-07 https://scifaro.com/en/abs/polystore-accelerated-polystore-system-for-heterogeneous-workloads-1905.103362019-05-27 https://scifaro.com/en/abs/indicating-asynchronous-multipliers-1905.112312019-05-28 https://scifaro.com/en/abs/ivams-1-0-polynomial-metamodel-integrated-intelligent-verilog-ams-for-fast-accurate-mixed-signal-design-optimization-1905.128122019-05-31 https://scifaro.com/en/abs/sparse-matrix-to-matrix-multiplication-a-representation-and-architecture-for-acceleration-long-version-1906.003272019-06-04 https://scifaro.com/en/abs/ara-a-1-ghz-scalable-and-energy-efficient-risc-v-vector-processor-with-multi-precision-floating-point-support-in-22-nm-fd-soi-1906.004782022-07-20 https://scifaro.com/en/abs/pangloss-a-novel-markov-chain-prefetcher-1906.008772019-06-04 https://scifaro.com/en/abs/thread-batching-for-high-performance-energy-efficient-gpu-memory-design-1906.059222019-06-17 https://scifaro.com/en/abs/an-overview-of-in-memory-processing-with-emerging-non-volatile-memory-for-data-intensive-applications-1906.066032019-06-18 https://scifaro.com/en/abs/a-retrospective-recount-of-computer-architecture-research-with-a-data-driven-study-of-over-four-decades-of-isca-publications-1906.093802019-06-25 https://scifaro.com/en/abs/automatic-conversion-from-flip-flop-to-3-phase-latch-based-designs-1906.106662019-06-26 https://scifaro.com/en/abs/fpga-based-multi-chip-module-for-high-performance-computing-1906.111752019-06-27 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https://scifaro.com/en/abs/fast-modeling-l2-cache-reuse-distance-histograms-using-combined-locality-information-from-software-traces-1907.050682020-10-13 https://scifaro.com/en/abs/coprocessors-failures-and-successes-1907.069482019-07-17 https://scifaro.com/en/abs/cads-core-aware-dynamic-scheduler-for-multicore-memory-controllers-1907.077762019-07-19 https://scifaro.com/en/abs/ppac-a-versatile-in-memory-accelerator-for-matrix-vector-product-like-operations-1907.086412019-07-23 https://scifaro.com/en/abs/reconfigurable-multiplier-architecture-based-on-memristor-cmos-with-higher-flexibility-1907.090782019-07-23 https://scifaro.com/en/abs/performance-comparison-of-quasi-delay-insensitive-asynchronous-adders-1907.108262019-07-26 https://scifaro.com/en/abs/mixed-level-identification-of-fault-redundancy-in-microprocessors-1907.123252019-07-30 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https://scifaro.com/en/abs/high-level-combined-deterministic-and-pseudoexhuastive-test-generation-for-risc-processors-1908.029862019-09-04 https://scifaro.com/en/abs/work-in-progress-a-simulation-framework-for-domain-specific-system-on-chips-1908.036642019-08-13 https://scifaro.com/en/abs/near-data-acceleration-with-concurrent-host-access-1908.063622020-12-02 https://scifaro.com/en/abs/workload-aware-opportunistic-energy-efficiency-in-multi-fpga-platforms-1908.065192019-10-30 https://scifaro.com/en/abs/boosting-the-bounds-of-symbolic-qed-for-effective-pre-silicon-verification-of-processor-cores-1908.067572021-06-18 https://scifaro.com/en/abs/ternary-circuits-why-r-3-is-not-the-optimal-radix-for-computation-1908.068412019-08-20 https://scifaro.com/en/abs/comparing-ternary-and-binary-adders-and-multipliers-1908.072992019-08-21 https://scifaro.com/en/abs/a-bi-directional-address-event-transceiver-block-for-low-latency-inter-chip-communication-in-neuromorphic-systems-1908.074132019-08-21 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https://scifaro.com/en/abs/rvcorep-an-optimized-risc-v-soft-processor-of-five-stage-pipelining-2002.035682020-12-30 https://scifaro.com/en/abs/a-portable-and-linux-capable-risc-v-computer-system-in-verilog-hdl-2002.035762020-03-30 https://scifaro.com/en/abs/rainbow-a-composable-coherence-protocol-for-multi-chip-servers-2002.039442024-05-06 https://scifaro.com/en/abs/functional-failure-rate-due-to-single-event-transients-in-clock-distribution-networks-2002.054552020-02-14 https://scifaro.com/en/abs/rapidlayout-fast-hard-block-placement-of-fpga-optimized-systolic-arrays-using-evolutionary-algorithms-2002.069982020-07-21 https://scifaro.com/en/abs/design-of-sec-ded-and-sec-ded-daec-codes-of-different-lengths-2002.075072020-02-19 https://scifaro.com/en/abs/sparch-efficient-architecture-for-sparse-matrix-multiplication-2002.089472024-04-05 https://scifaro.com/en/abs/snitch-a-tiny-pseudo-dual-issue-processor-for-area-and-energy-efficient-execution-of-floating-point-intensive-workloads-2002.101432020-10-09 https://scifaro.com/en/abs/lorax-loss-aware-approximations-for-energy-efficient-silicon-photonic-networks-on-chip-2002.112892020-02-27 https://scifaro.com/en/abs/a-compiler-infrastructure-for-fpga-and-asic-development-2003.001512020-03-03 https://scifaro.com/en/abs/luxor-an-fpga-logic-cell-architecture-for-efficient-compressor-tree-implementations-2003.030432020-03-09 https://scifaro.com/en/abs/cycle-accurate-evaluation-of-software-hardware-co-design-of-decimal-computation-in-risc-v-ecosystem-2003.053152020-03-12 https://scifaro.com/en/abs/new-approximate-multiplier-for-low-power-digital-signal-processing-2003.067272020-03-17 https://scifaro.com/en/abs/report-on-power-thermal-and-reliability-prediction-for-3d-networks-on-chip-2003.086482020-03-20 https://scifaro.com/en/abs/ds3-a-system-level-domain-specific-system-on-chip-simulation-framework-2003.090162020-03-23 https://scifaro.com/en/abs/soft-error-and-hard-fault-tolerant-architecture-and-routing-algorithm-for-reliable-3d-noc-systems-2003.096162020-03-24 https://scifaro.com/en/abs/reliability-assessment-and-quantitative-evaluation-of-soft-error-resilient-3d-network-on-chip-systems-2003.096172020-03-24 https://scifaro.com/en/abs/a-distributed-memory-local-configuration-technique-for-re-configurable-logic-designs-2003.104722020-03-25 https://scifaro.com/en/abs/a-low-overhead-soft-hard-fault-tolerant-architecture-design-and-management-scheme-for-reliable-high-performance-many-core-3d-noc-systems-2003.110182020-03-25 https://scifaro.com/en/abs/verification-and-design-methods-for-the-brainscales-neuromorphic-hardware-system-2003.114552020-03-26 https://scifaro.com/en/abs/analytical-model-of-memory-bound-applications-compiled-with-high-level-synthesis-2003.130542020-03-31 https://scifaro.com/en/abs/efficient-implementation-of-multi-channel-convolution-in-monolithic-3d-reram-crossbar-2004.002432020-04-02 https://scifaro.com/en/abs/hardware-trojan-with-frequency-modulation-2004.013532020-04-06 https://scifaro.com/en/abs/hardware-trojan-detection-using-controlled-circuit-aging-2004.029972020-11-13 https://scifaro.com/en/abs/esp4ml-platform-based-design-of-systems-on-chip-for-embedded-machine-learning-2004.036402020-06-19 https://scifaro.com/en/abs/hybriddnn-a-framework-for-high-performance-hybrid-dnn-accelerator-design-and-implementation-2004.038042020-04-09 https://scifaro.com/en/abs/a-survey-on-coarse-grained-reconfigurable-architectures-from-a-performance-perspective-2004.045092020-09-16 https://scifaro.com/en/abs/smart-paths-for-latency-reduction-in-reram-processing-in-memory-architecture-for-cnn-inference-2004.048652020-04-13 https://scifaro.com/en/abs/hardware-memory-management-for-future-mobile-hybrid-memory-systems-2004.055182024-03-19 https://scifaro.com/en/abs/energy-efficient-hardware-accelerated-synchronization-for-shared-l1-memory-multiprocessor-clusters-2004.066622020-04-15 https://scifaro.com/en/abs/the-mosaicsim-simulator-full-technical-report-2004.074152020-04-17 https://scifaro.com/en/abs/bridging-the-gap-fpgas-as-programmable-switches-2004.077332020-04-17 https://scifaro.com/en/abs/towards-a-hardware-dsl-ecosystem-rubyrtl-and-friends-2004.098582020-04-22 https://scifaro.com/en/abs/nom-network-on-memory-for-inter-bank-data-transfer-in-highly-banked-memories-2004.099232020-04-27 https://scifaro.com/en/abs/pmevo-portable-inference-of-port-mappings-for-out-of-order-processors-by-evolutionary-optimization-2004.100442020-04-22 https://scifaro.com/en/abs/drmap-a-generic-dram-data-mapping-policy-for-energy-efficient-processing-of-convolutional-neural-networks-2004.103412023-03-06 https://scifaro.com/en/abs/proactive-aging-mitigation-in-cgras-through-utilization-aware-allocation-2004.104702020-11-06 https://scifaro.com/en/abs/using-libraries-of-approximate-circuits-in-design-of-hardware-accelerators-of-deep-neural-networks-2004.104832020-07-06 https://scifaro.com/en/abs/approxfpgas-embracing-asic-based-approximate-arithmetic-components-for-fpga-based-systems-2004.105022020-12-29 https://scifaro.com/en/abs/using-dsp-slices-as-content-addressable-update-queues-2004.110802020-04-24 https://scifaro.com/en/abs/the-case-for-learning-application-behavior-to-improve-hardware-energy-efficiency-2004.130742020-11-25 https://scifaro.com/en/abs/run-time-accuracy-reconfigurable-stochastic-computing-for-dynamic-reliability-and-power-management-2004.133202020-04-29 https://scifaro.com/en/abs/electromigration-aware-architecture-for-modern-microprocessors-2005.015932021-09-14 https://scifaro.com/en/abs/best-implementations-of-quaternary-adders-2005.022062020-05-06 https://scifaro.com/en/abs/testing-compilers-for-programmable-switches-through-switch-hardware-simulation-2005.023102020-10-29 https://scifaro.com/en/abs/litex-an-open-source-soc-builder-and-library-based-on-migen-python-dsl-2005.025062020-05-07 https://scifaro.com/en/abs/a-post-silicon-trace-analysis-approach-for-system-on-chip-protocol-debug-2005.025502020-05-07 https://scifaro.com/en/abs/comparing-quaternary-and-binary-multipliers-2005.026782020-05-07 https://scifaro.com/en/abs/benchmarking-high-bandwidth-memory-on-fpgas-2005.043242020-05-12 https://scifaro.com/en/abs/exploiting-inter-and-intra-memory-asymmetries-for-data-mapping-in-hybrid-tiered-memories-2005.047502020-05-12 https://scifaro.com/en/abs/improving-phase-change-memory-performance-with-data-content-aware-access-2005.047532020-05-12 https://scifaro.com/en/abs/sysscale-exploiting-multi-domain-dynamic-voltage-and-frequency-scaling-for-energy-efficient-mobile-processors-2005.076132020-05-19 https://scifaro.com/en/abs/energy-efficient-on-chip-networks-through-profiled-hybrid-switching-2005.084782020-05-19 https://scifaro.com/en/abs/the-virtual-block-interface-a-flexible-alternative-to-the-conventional-virtual-memory-framework-2005.097482020-05-21 https://scifaro.com/en/abs/stack-up-your-chips-betting-on-3d-integration-to-augment-moore-s-law-scaling-2005.108662020-05-25 https://scifaro.com/en/abs/accelerate-cycle-level-full-system-simulation-of-multi-core-risc-v-systems-with-binary-translation-2005.113572020-05-26 https://scifaro.com/en/abs/clr-dram-a-low-cost-dram-architecture-enabling-dynamic-capacity-latency-trade-off-2005.127752020-05-27 https://scifaro.com/en/abs/revisiting-rowhammer-an-experimental-analysis-of-modern-dram-devices-and-mitigation-techniques-2005.131212020-06-01 https://scifaro.com/en/abs/dynamic-merge-point-prediction-2005.146912020-06-01 https://scifaro.com/en/abs/clarinet-a-risc-v-based-framework-for-posit-arithmetic-empiricism-2006.003642021-10-28 https://scifaro.com/en/abs/how-to-extend-the-single-processor-paradigm-to-the-explicitly-many-processor-approach-2006.005322020-06-02 https://scifaro.com/en/abs/exceeding-conservative-limits-a-consolidated-analysis-on-modern-hardware-margins-2006.010492020-06-02 https://scifaro.com/en/abs/operation-merging-for-hardware-implementations-of-fast-polar-decoders-2006.020122020-06-04 https://scifaro.com/en/abs/a-gpu-register-file-using-static-data-compression-2006.056932020-12-10 https://scifaro.com/en/abs/unified-characterization-platform-for-emerging-nvm-technology-neural-network-application-benchmarking-using-off-the-shelf-nvm-chips-2006.056962020-06-11 https://scifaro.com/en/abs/a-unified-learning-platform-for-dynamic-frequency-scaling-in-pipelined-processors-2006.074502020-06-16 https://scifaro.com/en/abs/architecture-support-for-fpga-multi-tenancy-in-the-cloud-2006.080262020-06-16 https://scifaro.com/en/abs/addressing-variability-in-reuse-prediction-for-last-level-caches-2006.084872020-06-16 https://scifaro.com/en/abs/zng-architecting-gpu-multi-processors-with-new-flash-for-scalable-data-analysis-2006.089752020-06-17 https://scifaro.com/en/abs/design-of-a-near-ideal-fault-tolerant-routing-algorithm-for-network-on-chip-based-multicores-2006.110252020-06-22 https://scifaro.com/en/abs/compiler-directed-speculative-intermittent-computation-2006.114792020-06-23 https://scifaro.com/en/abs/optimizing-placement-of-heap-memory-objects-in-energy-constrained-hybrid-memory-systems-2006.121332020-06-24 https://scifaro.com/en/abs/scare-side-channel-attack-on-in-memory-computing-for-reverse-engineering-2006.130952020-06-24 https://scifaro.com/en/abs/fetch-directed-instruction-prefetching-revisited-2006.135472020-06-25 https://scifaro.com/en/abs/on-the-difficulty-of-designing-processor-arrays-for-deep-neural-networks-2006.140082020-06-26 https://scifaro.com/en/abs/arnold-an-efpga-augmented-risc-v-soc-for-flexible-and-low-power-iot-end-nodes-2006.142562020-06-26 https://scifaro.com/en/abs/a-fast-finite-field-multiplier-for-sike-2006.143172020-11-30 https://scifaro.com/en/abs/rcp-a-low-overhead-reversible-coherence-protocol-2006.165352022-07-26 https://scifaro.com/en/abs/tdo-cim-transparent-detection-and-offloading-for-computation-in-memory-2007.000602020-07-02 https://scifaro.com/en/abs/enabling-compute-communication-overlap-in-distributed-deep-learning-training-platforms-2007.001562022-05-05 https://scifaro.com/en/abs/hardware-acceleration-of-sparse-and-irregular-tensor-computations-of-ml-models-a-survey-and-insights-2007.008642021-08-11 https://scifaro.com/en/abs/efficient-neural-network-deployment-for-microcontroller-2007.013482020-07-06 https://scifaro.com/en/abs/deep-powerx-a-deep-learning-based-framework-for-low-power-approximate-logic-synthesis-2007.014652020-07-06 https://scifaro.com/en/abs/fpnew-an-open-source-multi-format-floating-point-unit-architecture-for-energy-proportional-transprecision-computing-2007.015302020-07-06 https://scifaro.com/en/abs/a-machine-learning-pipeline-stage-for-adaptive-frequency-adjustment-2007.018202020-07-06 https://scifaro.com/en/abs/a-ring-router-microarchitecture-for-nocs-2007.022422020-07-07 https://scifaro.com/en/abs/the-gem5-simulator-version-20-0-2007.031522020-10-01 https://scifaro.com/en/abs/halcone-a-hardware-level-timestamp-based-cache-coherence-scheme-for-multi-gpu-systems-2007.042922020-07-09 https://scifaro.com/en/abs/ioca-high-speed-i-o-aware-llc-management-for-network-centric-multi-tenant-platform-2007.045522021-03-05 https://scifaro.com/en/abs/hardware-implementation-of-deep-network-accelerators-towards-healthcare-and-biomedical-applications-2007.056572021-04-29 https://scifaro.com/en/abs/hobflops-cnns-hardware-optimized-bitslice-parallel-floating-point-operations-for-convolutional-neural-networks-2007.065632021-03-02 https://scifaro.com/en/abs/irregular-accesses-reorder-unit-improving-gpgpu-memory-coalescing-for-graph-based-workloads-2007.071312022-03-17 https://scifaro.com/en/abs/enabling-mixed-precision-quantized-neural-networks-in-extreme-edge-devices-2007.077592020-07-16 https://scifaro.com/en/abs/a-survey-of-aging-monitors-and-reconfiguration-techniques-2007.078292020-07-16 https://scifaro.com/en/abs/dagger-towards-efficient-rpcs-in-cloud-microservices-with-near-memory-reconfigurable-nics-2007.086222020-09-14 https://scifaro.com/en/abs/always-on-674uw-4gop-s-error-resilient-binary-neural-networks-with-aggressive-sram-voltage-scaling-on-a-22nm-iot-end-node-2007.089522020-07-20 https://scifaro.com/en/abs/klessydra-t-designing-vector-coprocessors-for-multi-threaded-edge-computing-cores-2007.091092021-02-09 https://scifaro.com/en/abs/runtime-task-scheduling-using-imitation-learning-for-heterogeneous-many-core-systems-2007.093612020-08-10 https://scifaro.com/en/abs/design-space-exploration-of-algorithmic-multi-port-memories-in-high-performance-application-specific-accelerators-2007.093632022-09-07 https://scifaro.com/en/abs/deepdive-an-integrative-algorithm-architecture-co-design-for-deep-separable-convolutional-neural-networks-2007.094902020-07-21 https://scifaro.com/en/abs/neuromax-a-high-throughput-multi-threaded-log-based-accelerator-for-convolutional-neural-networks-2007.095782020-07-21 https://scifaro.com/en/abs/uvmbench-a-comprehensive-benchmark-suite-for-researching-unified-virtual-memory-in-gpus-2007.098222020-10-22 https://scifaro.com/en/abs/energy-efficient-computing-systems-architectures-abstractions-and-modeling-to-techniques-and-standards-2007.099762022-03-24 https://scifaro.com/en/abs/hpipe-heterogeneous-layer-pipelined-and-sparse-aware-cnn-inference-for-fpgas-2007.104512020-07-22 https://scifaro.com/en/abs/exploiting-process-variations-to-secure-photonic-noc-architectures-from-snooping-attacks-2007.104542020-07-22 https://scifaro.com/en/abs/tcim-triangle-counting-acceleration-with-processing-in-mram-architecture-2007.107022020-07-22 https://scifaro.com/en/abs/analytical-modeling-the-multi-core-shared-cache-behavior-with-considerations-of-data-sharing-and-coherence-2007.111952020-10-20 https://scifaro.com/en/abs/speculative-interference-attacks-breaking-invisible-speculation-schemes-2007.118182021-04-26 https://scifaro.com/en/abs/comparative-analysis-of-polynomial-and-rational-approximations-of-hyperbolic-tangent-function-for-vlsi-implementation-2007.119762020-09-25 https://scifaro.com/en/abs/hardware-implementation-of-hyperbolic-tangent-function-using-catmull-rom-spline-interpolation-2007.135162020-07-28 https://scifaro.com/en/abs/caram-a-content-aware-hybrid-pcm-dram-main-memory-system-framework-2007.136612020-07-28 https://scifaro.com/en/abs/performance-aware-predictive-model-based-on-chip-body-bias-regulation-strategy-for-an-ulp-multi-core-cluster-in-28nm-utbb-fd-soi-2007.136672020-07-31 https://scifaro.com/en/abs/grip-a-graph-neural-network-accelerator-architecture-2007.138282020-07-31 https://scifaro.com/en/abs/stomp-a-tool-for-evaluation-of-scheduling-policies-in-heterogeneous-multi-processors-2007.143712020-07-29 https://scifaro.com/en/abs/transaction-level-model-simulator-for-communication-limited-accelerators-2007.148972020-07-30 https://scifaro.com/en/abs/fast-thresholded-sc-flip-decoding-of-polar-codes-2007.156472020-07-31 https://scifaro.com/en/abs/optimal-layout-synthesis-for-quantum-computing-2007.156712023-05-30 https://scifaro.com/en/abs/thermal-analysis-of-a-3d-stacked-high-performance-commercial-microprocessor-using-face-to-face-wafer-bonding-technology-2007.161792020-08-03 https://scifaro.com/en/abs/partial-reconfiguration-for-design-optimization-2008.000622020-08-04 https://scifaro.com/en/abs/intelligent-management-of-mobile-systems-through-computational-self-awareness-2008.000952020-08-04 https://scifaro.com/en/abs/deact-architecture-aware-virtual-memory-support-for-fabric-attached-memory-systems-2008.001712020-08-04 https://scifaro.com/en/abs/custom-tailored-suite-of-random-forests-for-prefetcher-adaptation-2008.001762020-08-04 https://scifaro.com/en/abs/cuttlesys-data-driven-resource-management-forinteractive-applications-on-reconfigurable-multicores-2008.003292020-08-04 https://scifaro.com/en/abs/damo-deep-agile-mask-optimization-for-full-chip-scale-2008.008062020-11-17 https://scifaro.com/en/abs/accelerating-genome-analysis-a-primer-on-an-ongoing-journey-2008.009612020-10-29 https://scifaro.com/en/abs/optimum-reconfiguration-of-routing-interconnection-network-in-apsoc-fabrics-2008.018692020-08-06 https://scifaro.com/en/abs/a-novel-method-for-scalable-vlsi-implementation-of-hyperbolic-tangent-function-2008.020782021-03-05 https://scifaro.com/en/abs/mgpu-tsm-a-multi-gpu-system-with-truly-shared-memory-2008.023002020-08-11 https://scifaro.com/en/abs/design-of-reconfigurable-multi-operand-adder-for-massively-parallel-processing-2008.025842020-08-10 https://scifaro.com/en/abs/helix-algorithm-architecture-co-design-for-accelerating-nanopore-genome-base-calling-2008.031072020-08-10 https://scifaro.com/en/abs/design-space-exploration-of-power-delivery-for-advanced-packaging-technologies-2008.031242020-08-10 https://scifaro.com/en/abs/bit-parallel-6t-sram-in-memory-computing-with-reconfigurable-bit-precision-2008.033782020-08-11 https://scifaro.com/en/abs/sealing-neural-network-models-in-secure-deep-learning-accelerators-2008.037522020-08-11 https://scifaro.com/en/abs/ising-model-optimization-problems-on-a-fpga-accelerated-restricted-boltzmann-machine-2008.044362020-10-15 https://scifaro.com/en/abs/area-optimized-quasi-delay-insensitive-majority-voter-for-tmr-applications-2008.056852020-08-14 https://scifaro.com/en/abs/intelligent-architectures-for-intelligent-machines-2008.061122020-08-17 https://scifaro.com/en/abs/panda-processing-in-mram-accelerated-de-bruijn-graph-based-dna-assembly-2008.061772020-08-17 https://scifaro.com/en/abs/manticore-a-4096-core-risc-v-chiplet-architecture-for-ultra-efficient-floating-point-computing-2008.065022020-11-23 https://scifaro.com/en/abs/breaking-barriers-maximizing-array-utilization-for-compute-in-memory-fabrics-2008.067412020-08-18 https://scifaro.com/en/abs/cargo-context-augmented-critical-region-offload-for-network-bound-datacenter-workloads-2008.071712020-08-18 https://scifaro.com/en/abs/ptolemy-architecture-support-for-robust-deep-learning-2008.099542020-08-25 https://scifaro.com/en/abs/tearing-down-the-memory-wall-2008.101692020-08-25 https://scifaro.com/en/abs/evaluation-of-hybrid-run-time-power-models-for-the-arm-big-little-architecture-2008.106042020-08-26 https://scifaro.com/en/abs/align-a-system-for-automating-analog-layout-2008.106822026-01-26 https://scifaro.com/en/abs/optically-connected-memory-for-disaggregated-data-centers-2008.108022020-08-26 https://scifaro.com/en/abs/mitigating-the-latency-area-tradeoffs-for-dram-design-with-coarse-grained-monolithic-3d-m3d-integration-2008.113672020-08-27 https://scifaro.com/en/abs/an-approximate-carry-estimating-simultaneous-adder-with-rectification-2008.115912020-09-01 https://scifaro.com/en/abs/an-8-bit-in-resistive-memory-computing-core-with-regulated-passive-neuron-and-bit-line-weight-mapping-2008.116692020-08-27 https://scifaro.com/en/abs/dnnexplorer-a-framework-for-modeling-and-exploring-a-novel-paradigm-of-fpga-based-dnn-accelerator-2008.127452021-03-25 https://scifaro.com/en/abs/architectural-analysis-of-fpga-technology-impact-2008.134302020-09-01 https://scifaro.com/en/abs/machine-learning-clustering-techniques-for-selective-mitigation-of-critical-design-features-2008.136642021-04-05 https://scifaro.com/en/abs/helper-without-threads-customized-prefetching-for-delinquent-irregular-loads-2009.002022020-09-02 https://scifaro.com/en/abs/risc-micrprocessor-verification-2009.002232020-09-02 https://scifaro.com/en/abs/reversible-computing-with-fast-fully-static-fully-adiabatic-cmos-2009.004482020-09-03 https://scifaro.com/en/abs/direct-cmos-implementation-of-neuromorphic-temporal-neural-networks-for-sensory-processing-2009.004572020-09-02 https://scifaro.com/en/abs/a-survey-on-recent-hardware-data-prefetching-approaches-with-an-emphasis-on-servers-2009.007152020-09-03 https://scifaro.com/en/abs/tensordash-exploiting-sparsity-to-accelerate-deep-neural-network-training-and-inference-2009.007482022-03-28 https://scifaro.com/en/abs/architectural-implications-of-graph-neural-networks-2009.008042021-12-28 https://scifaro.com/en/abs/hl-pow-a-learning-based-power-modeling-framework-for-high-level-synthesis-2009.008712020-09-03 https://scifaro.com/en/abs/contra-area-constrained-technology-mapping-framework-for-memristive-memory-processing-unit-2009.008812020-09-03 https://scifaro.com/en/abs/agile-soc-development-with-open-esp-2009.011782020-09-03 https://scifaro.com/en/abs/an-ensemble-learning-approach-for-in-situ-monitoring-of-fpga-dynamic-power-2009.014322020-09-04 https://scifaro.com/en/abs/decision-tree-based-hardware-power-monitoring-for-run-time-dynamic-power-management-in-fpga-2009.014342020-09-04 https://scifaro.com/en/abs/scalable-light-weight-integration-of-fpga-based-accelerators-with-chip-multi-processors-2009.014412020-09-04 https://scifaro.com/en/abs/confuciux-autonomous-hardware-resource-assignment-for-dnn-accelerators-using-reinforcement-learning-2009.020102020-09-07 https://scifaro.com/en/abs/sparse-systolic-tensor-array-for-efficient-cnn-hardware-acceleration-2009.023812020-10-14 https://scifaro.com/en/abs/polyadd-polynomial-formal-verification-of-adder-circuits-2009.032422021-04-06 https://scifaro.com/en/abs/quad-core-rsa-processor-with-countermeasure-against-power-analysis-attacks-2009.034682020-09-09 https://scifaro.com/en/abs/asymmetric-aging-effect-on-modern-microprocessors-2009.039452020-09-10 https://scifaro.com/en/abs/development-of-a-predictive-process-design-kit-for15-nm-finfets-freepdk15-2009.046002020-09-11 https://scifaro.com/en/abs/micrograd-a-centralized-framework-for-workload-cloning-and-stress-testing-2009.046222020-09-11 https://scifaro.com/en/abs/accelerating-recommender-systems-via-hardware-scale-in-2009.052302020-09-14 https://scifaro.com/en/abs/dmr-based-technique-for-fault-tolerant-aes-s-box-architecture-2009.053292020-09-14 https://scifaro.com/en/abs/an-open-source-platform-for-high-performance-non-coherent-on-chip-communication-2009.053342021-11-12 https://scifaro.com/en/abs/the-cost-of-software-based-memory-management-without-virtual-memory-2009.067892020-09-16 https://scifaro.com/en/abs/secure-internal-communication-of-a-trustzone-enabled-heterogeneous-soc-lightweight-encryption-2009.068962020-09-16 https://scifaro.com/en/abs/genasm-a-high-performance-low-power-approximate-string-matching-acceleration-framework-for-genome-sequence-analysis-2009.076922020-09-17 https://scifaro.com/en/abs/enabling-virtual-memory-research-on-risc-v-with-a-configurable-tlb-hierarchy-for-the-rocket-chip-generator-2009.077232020-09-17 https://scifaro.com/en/abs/bit-exact-ecc-recovery-beer-determining-dram-on-die-ecc-functions-by-exploiting-dram-data-retention-characteristics-2009.079852020-09-18 https://scifaro.com/en/abs/nero-a-near-high-bandwidth-memory-stencil-accelerator-for-weather-prediction-modeling-2009.082412020-09-18 https://scifaro.com/en/abs/figaro-improving-system-performance-via-fine-grained-in-dram-data-relocation-and-caching-2009.084372020-09-18 https://scifaro.com/en/abs/thermal-and-ir-drop-analysis-using-convolutional-encoder-decoder-networks-2009.090092020-09-22 https://scifaro.com/en/abs/load-driven-branch-predictor-ldbp-2009.090642020-09-22 https://scifaro.com/en/abs/open-source-synthesizable-analog-blocks-for-high-speed-link-designs-20-gs-s-5b-enob-analog-to-digital-converter-and-5-ghz-phase-interpolator-2009.090772020-09-22 https://scifaro.com/en/abs/flexwatts-a-power-and-workload-aware-hybrid-power-delivery-network-for-energy-efficient-microprocessors-2009.090942020-09-22 https://scifaro.com/en/abs/tb-s-polar-successive-cancellation-decoder-16nm-asic-implementation-2009.093882020-09-22 https://scifaro.com/en/abs/a-survey-of-resource-management-for-processing-in-memory-and-near-memory-processing-architectures-2009.096032020-09-22 https://scifaro.com/en/abs/a-high-performance-memristor-based-smith-waterman-dna-sequence-alignment-using-fpni-structure-2009.097872020-09-22 https://scifaro.com/en/abs/extending-high-level-synthesis-for-task-parallel-programs-2009.113892021-05-07 https://scifaro.com/en/abs/a-study-of-runtime-adaptive-prefetching-for-sttram-l1-caches-2009.114422020-09-25 https://scifaro.com/en/abs/new-categories-of-safe-faults-in-a-processor-based-embedded-system-2009.116212020-09-25 https://scifaro.com/en/abs/rubik-a-hierarchical-architecture-for-efficient-graph-learning-2009.124952020-09-29 https://scifaro.com/en/abs/particle-mesh-ewald-for-molecular-dynamics-in-opencl-on-an-fpga-cluster-2009.126172021-04-06 https://scifaro.com/en/abs/breaking-the-memory-wall-for-ai-chip-with-a-new-dimension-2009.136642020-09-30 https://scifaro.com/en/abs/autodse-enabling-software-programmers-to-design-efficient-fpga-accelerators-2009.143812021-09-01 https://scifaro.com/en/abs/system-measurement-of-intel-aep-optane-dimm-2009.144692020-10-01 https://scifaro.com/en/abs/an-embedded-risc-v-core-with-fast-modular-multiplication-2009.146852020-10-01 https://scifaro.com/en/abs/carla-a-convolution-accelerator-with-a-reconfigurable-and-low-energy-architecture-2010.006272020-10-05 https://scifaro.com/en/abs/synchronizer-free-digital-link-controller-2010.020172020-10-06 https://scifaro.com/en/abs/natsa-a-near-data-processing-accelerator-for-time-series-analysis-2010.020792020-10-08 https://scifaro.com/en/abs/wolfram-enhancing-wear-leveling-and-fault-tolerance-in-resistive-memories-using-programmable-address-decoders-2010.028252020-10-07 https://scifaro.com/en/abs/a-hardware-aware-heuristic-for-the-qubit-mapping-problem-in-the-nisq-era-2010.033972020-10-08 https://scifaro.com/en/abs/a-mixed-precision-risc-v-processor-for-extreme-edge-dnn-inference-2010.040732020-10-09 https://scifaro.com/en/abs/an-energy-efficient-low-voltage-swing-transceiver-for-mw-range-iot-end-nodes-2010.045662020-10-12 https://scifaro.com/en/abs/cross-stack-workload-characterization-of-deep-recommendation-systems-2010.050372020-10-13 https://scifaro.com/en/abs/taxonn-a-light-weight-accelerator-for-deep-neural-network-training-2010.051972020-10-13 https://scifaro.com/en/abs/microrec-efficient-recommendation-inference-by-hardware-and-data-structure-solutions-2010.058942021-02-22 https://scifaro.com/en/abs/when-hls-meets-fpga-hbm-benchmarking-and-bandwidth-optimization-2010.060752020-10-14 https://scifaro.com/en/abs/high-area-energy-efficiency-rram-cnn-accelerator-with-kernel-reordering-weight-mapping-scheme-based-on-pattern-pruning-2010.061562020-10-14 https://scifaro.com/en/abs/piuma-programmable-integrated-unified-memory-architecture-2010.062772025-03-03 https://scifaro.com/en/abs/effective-algorithm-accelerator-co-design-for-ai-solutions-on-edge-devices-2010.071852020-10-16 https://scifaro.com/en/abs/fpraker-a-processing-element-for-accelerating-neural-network-training-2010.080652020-10-19 https://scifaro.com/en/abs/combinatorics-and-geometry-for-the-many-ported-distributed-and-shared-memory-architecture-2010.086672020-10-20 https://scifaro.com/en/abs/enabling-high-capacity-latency-tolerant-and-highly-concurrent-gpu-register-files-via-software-hardware-cooperation-2010.093302020-10-20 https://scifaro.com/en/abs/closed-loop-neural-interfaces-with-embedded-machine-learning-2010.094572020-10-22 https://scifaro.com/en/abs/a-risc-v-systemc-tlm-simulator-2010.101192020-10-21 https://scifaro.com/en/abs/eliminating-the-barriers-demystifying-wi-fi-baseband-design-and-introducing-the-picoscenes-wi-fi-sensing-platform-2010.102332021-08-13 https://scifaro.com/en/abs/slim-noc-a-low-diameter-on-chip-network-topology-for-high-energy-efficiency-and-scalability-2010.106832020-10-22 https://scifaro.com/en/abs/the-nanopu-redesigning-the-cpu-network-interface-to-minimize-rpc-tail-latency-2010.121142020-10-26 https://scifaro.com/en/abs/efficient-floating-point-givens-rotation-unit-2010.123762020-10-26 https://scifaro.com/en/abs/mars-multi-macro-architecture-sram-cim-based-accelerator-with-co-designed-compressed-neural-networks-2010.128612021-05-26 https://scifaro.com/en/abs/expan-n-d-exploring-posits-for-efficient-artificial-neural-network-design-in-fpga-based-systems-2010.128692023-09-06 https://scifaro.com/en/abs/tensor-casting-co-designing-algorithm-architecture-for-personalized-recommendation-training-2010.131002020-10-27 https://scifaro.com/en/abs/hxdp-efficient-software-packet-processing-on-fpga-nics-2010.141452020-10-28 https://scifaro.com/en/abs/analysis-of-energy-consumption-in-a-precision-beekeeping-system-2010.149342020-10-29 https://scifaro.com/en/abs/rvcorep-32im-an-effective-architecture-to-implement-mul-div-instructions-for-five-stage-risc-v-soft-processors-2010.161712020-11-02 https://scifaro.com/en/abs/an-in-module-disturbance-barrier-for-mitigating-write-disturbance-in-phase-change-memory-2011.004482022-08-10 https://scifaro.com/en/abs/addressing-resiliency-of-in-memory-floating-point-computation-2011.006482020-11-03 https://scifaro.com/en/abs/on-the-impact-of-partial-sums-on-interconnect-bandwidth-and-memory-accesses-in-a-dnn-accelerator-2011.008502021-02-25 https://scifaro.com/en/abs/simdive-approximate-simd-soft-multiplier-divider-for-fpgas-with-tunable-accuracy-2011.011482020-11-03 https://scifaro.com/en/abs/cutie-beyond-petaop-s-w-ternary-dnn-inference-acceleration-with-better-than-binary-energy-efficiency-2011.017132021-02-05 https://scifaro.com/en/abs/booster-an-accelerator-for-gradient-boosting-decision-trees-2011.020222020-11-06 https://scifaro.com/en/abs/chasing-carbon-the-elusive-environmental-footprint-of-computing-2011.028392020-11-06 https://scifaro.com/en/abs/refloat-low-cost-floating-point-processing-in-reram-for-accelerating-iterative-linear-solvers-2011.031902023-10-18 https://scifaro.com/en/abs/ehap-oram-efficient-hardware-assisted-persistent-oram-system-for-non-volatile-memory-2011.036692023-01-03 https://scifaro.com/en/abs/towards-latency-aware-dnn-optimization-with-gpu-runtime-analysis-and-tail-effect-elimination-2011.038972020-12-02 https://scifaro.com/en/abs/fpga-based-hyrbid-memory-emulation-system-2011.045672024-03-19 https://scifaro.com/en/abs/von-neumann-s-missing-second-draft-what-it-should-contain-2011.047272020-11-11 https://scifaro.com/en/abs/understanding-training-efficiency-of-deep-learning-recommendation-models-at-scale-2011.054972020-11-12 https://scifaro.com/en/abs/customizing-trusted-ai-accelerators-for-efficient-privacy-preserving-machine-learning-2011.063762020-11-13 https://scifaro.com/en/abs/memory-efficient-dataflow-inference-for-deep-cnns-on-fpga-2011.073172020-11-17 https://scifaro.com/en/abs/indirection-stream-semantic-register-architecture-for-efficient-sparse-dense-linear-algebra-2011.080702020-12-15 https://scifaro.com/en/abs/axes-approximation-manager-for-emerging-memory-architectures-2011.083532020-11-18 https://scifaro.com/en/abs/optimizing-graph-processing-and-preprocessing-with-hardware-assisted-propagation-blocking-2011.084512020-11-18 https://scifaro.com/en/abs/revising-the-classic-computing-paradigm-and-its-technological-implementations-2011.084552020-11-18 https://scifaro.com/en/abs/automatic-microprocessor-performance-bug-detection-2011.087812020-11-20 https://scifaro.com/en/abs/a-survey-of-system-architectures-and-techniques-for-fpga-virtualization-2011.090732021-02-22 https://scifaro.com/en/abs/arsmart-an-improved-smart-noc-design-supporting-arbitrary-turn-transmission-2011.092612020-11-19 https://scifaro.com/en/abs/azp-automatic-specialization-for-zero-values-in-gaming-applications-2011.105502020-11-23 https://scifaro.com/en/abs/third-archedge-workshop-exploring-the-design-space-of-efficient-deep-neural-networks-2011.109122020-11-24 https://scifaro.com/en/abs/copernicus-characterizing-the-performance-implications-of-compression-formats-used-in-sparse-workloads-2011.109322023-05-12 https://scifaro.com/en/abs/rvcorep-32ic-a-high-performance-risc-v-soft-processor-with-an-efficient-fetch-unit-supporting-the-compressed-instructions-2011.112462020-11-24 https://scifaro.com/en/abs/proximu-efficiently-scaling-dnn-inference-in-multi-core-cpus-through-near-cache-compute-2011.116952020-12-04 https://scifaro.com/en/abs/automated-floorplanning-for-partially-reconfigurable-designs-on-heterogenrous-fpgas-2011.117162020-11-25 https://scifaro.com/en/abs/accss3d-accelerator-for-spatially-sparse-3d-dnns-2011.126692020-11-26 https://scifaro.com/en/abs/low-latency-cmos-hardware-acceleration-for-fully-connected-layers-in-deep-neural-networks-2011.128392020-11-26 https://scifaro.com/en/abs/design-methodologies-for-reliable-and-energy-efficient-pcm-systems-2011.139592020-12-01 https://scifaro.com/en/abs/edgebert-sentence-level-energy-optimizations-for-latency-aware-multi-task-nlp-inference-2011.142032021-09-07 https://scifaro.com/en/abs/xpulpnn-enabling-energy-efficient-and-flexible-inference-of-quantized-neural-network-on-risc-v-based-iot-end-nodes-2011.143252020-12-01 https://scifaro.com/en/abs/dataflow-architecture-co-design-for-2-5d-dnn-accelerators-using-wireless-network-on-package-2011.147552020-12-01 https://scifaro.com/en/abs/aging-aware-request-scheduling-for-non-volatile-main-memory-2012.000502020-12-02 https://scifaro.com/en/abs/hem3d-heterogeneous-manycore-architecture-based-on-monolithic-3d-vertical-integration-2012.001022020-12-09 https://scifaro.com/en/abs/accelerating-bandwidth-bound-deep-learning-inference-with-main-memory-accelerators-2012.001582020-12-02 https://scifaro.com/en/abs/multivalued-circuits-and-interconnect-issues-2012.012672020-12-03 https://scifaro.com/en/abs/eudoxus-characterizing-and-accelerating-localization-in-autonomous-machines-2012.013532021-04-30 https://scifaro.com/en/abs/online-model-swapping-in-architectural-simulation-2012.015712020-12-04 https://scifaro.com/en/abs/characteristics-of-reversible-circuits-for-error-detection-2012.020372023-01-11 https://scifaro.com/en/abs/a-unified-model-for-gate-level-propagation-analysis-2012.027912020-12-08 https://scifaro.com/en/abs/towards-a-domain-specific-solution-for-a-new-generation-of-wireless-modems-2012.028902020-12-08 https://scifaro.com/en/abs/mempool-a-shared-l1-memory-many-core-cluster-with-a-low-latency-interconnect-2012.029732022-07-21 https://scifaro.com/en/abs/a-modern-primer-on-processing-in-memory-2012.031122025-02-07 https://scifaro.com/en/abs/systolic-cnn-an-opencl-defined-scalable-run-time-flexible-fpga-accelerator-architecture-for-accelerating-convolutional-neural-network-inference-in-cloud-edge-computing-2012.031772020-12-08 https://scifaro.com/en/abs/binarray-a-scalable-hardware-accelerator-for-binary-approximated-cnns-2012.034812021-04-13 https://scifaro.com/en/abs/fpga-deep-learning-acceleration-based-on-convolutional-neural-network-2012.036722020-12-08 https://scifaro.com/en/abs/deepnvm-cross-layer-modeling-and-optimization-framework-of-non-volatile-memories-for-deep-learning-2012.045592022-05-23 https://scifaro.com/en/abs/page-tables-keeping-them-flat-and-hot-cached-2012.050792021-09-03 https://scifaro.com/en/abs/efficient-bypass-in-mesh-and-torus-nocs-2012.051362020-12-11 https://scifaro.com/en/abs/virtual-link-a-scalable-multi-producer-multi-consumer-message-queue-architecture-for-cross-core-communication-2012.051812021-01-21 https://scifaro.com/en/abs/a-custom-7nm-cmos-standard-cell-library-for-implementing-tnn-based-neuromorphic-processors-2012.054192021-06-08 https://scifaro.com/en/abs/optimization-techniques-to-improve-inference-performance-of-a-forward-propagating-neural-network-on-an-fpga-2012.080712020-12-16 https://scifaro.com/en/abs/a-comparative-study-between-hls-and-hdl-on-soc-for-image-processing-applications-2012.083202020-12-16 https://scifaro.com/en/abs/spatten-efficient-sparse-attention-architecture-with-cascade-token-and-head-pruning-2012.098522024-07-22 https://scifaro.com/en/abs/mavirec-ml-aided-vectored-ir-dropestimation-and-classification-2012.105972020-12-22 https://scifaro.com/en/abs/intersectx-an-efficient-accelerator-for-graph-mining-2012.108482021-04-20 https://scifaro.com/en/abs/hardware-and-software-optimizations-for-accelerating-deep-neural-networks-survey-of-current-trends-challenges-and-the-road-ahead-2012.112332020-12-22 https://scifaro.com/en/abs/fantastic4-a-hardware-software-co-design-approach-for-efficiently-running-4bit-compact-multilayer-perceptrons-2012.113312020-12-22 https://scifaro.com/en/abs/cognitive-computing-in-data-centric-paradigm-2012.113342020-12-22 https://scifaro.com/en/abs/palmed-throughput-characterization-for-superscalar-architectures-extended-version-2012.114732022-01-19 https://scifaro.com/en/abs/simdram-a-framework-for-bit-serial-simd-processing-using-dram-2012.118902020-12-23 https://scifaro.com/en/abs/reducing-solid-state-drive-read-latency-by-optimizing-read-retry-extended-abstract-2012.121782021-03-15 https://scifaro.com/en/abs/intelligent-architectures-for-intelligent-computing-systems-2012.123812020-12-24 https://scifaro.com/en/abs/architecture-dataflow-and-physical-design-implications-of-3d-ics-for-dnn-accelerators-2012.125632021-02-19 https://scifaro.com/en/abs/edgedrnn-recurrent-neural-network-accelerator-for-edge-inference-2012.136002020-12-29 https://scifaro.com/en/abs/fundamental-limits-on-energy-delay-accuracy-of-in-memory-architectures-in-inference-applications-2012.136452020-12-29 https://scifaro.com/en/abs/data-criticality-in-multi-threaded-applications-an-insight-for-many-core-systems-2101.000552021-01-05 https://scifaro.com/en/abs/silicon-photonic-microring-based-chip-scale-accelerator-for-delayed-feedback-reservoir-computing-2101.005572021-01-05 https://scifaro.com/en/abs/db4hls-a-database-of-high-level-synthesis-design-space-explorations-2101.005872021-01-05 https://scifaro.com/en/abs/understanding-power-consumption-and-reliability-of-high-bandwidth-memory-with-voltage-underscaling-2101.009692021-01-05 https://scifaro.com/en/abs/design-of-a-dynamic-parameter-controlled-chaotic-prng-in-a-65nm-cmos-process-2101.011732021-01-06 https://scifaro.com/en/abs/high-level-fpga-accelerator-design-for-structured-mesh-based-explicit-numerical-solvers-2101.011772021-01-08 https://scifaro.com/en/abs/an-investigation-on-inherent-robustness-of-posit-data-representation-2101.014162021-01-06 https://scifaro.com/en/abs/best-cntfet-ternary-adders-2101.015162021-01-06 https://scifaro.com/en/abs/hardware-acceleration-of-hpc-computational-flow-dynamics-using-hbm-enabled-fpgas-2101.017452022-01-13 https://scifaro.com/en/abs/a-low-power-in-memory-multiplication-andaccumulation-array-with-modified-radix-4-inputand-canonical-signed-digit-weights-2101.024192021-01-08 https://scifaro.com/en/abs/brds-an-fpga-based-lstm-accelerator-with-row-balanced-dual-ratio-sparsification-2101.026672021-01-08 https://scifaro.com/en/abs/self-adaptive-reconfigurable-arrays-sara-using-ml-to-assist-scaling-gemm-acceleration-2101.047992022-04-26 https://scifaro.com/en/abs/exma-a-genomics-accelerator-for-exact-matching-2101.053142021-01-15 https://scifaro.com/en/abs/andromeda-an-fpga-based-risc-v-mpsoc-exploration-framework-2101.055912021-01-15 https://scifaro.com/en/abs/brightening-the-optical-flow-through-posit-arithmetic-2101.066652021-01-19 https://scifaro.com/en/abs/syncron-efficient-synchronization-support-for-near-data-processing-architectures-2101.075572021-02-16 https://scifaro.com/en/abs/cain-automatic-code-generation-for-simultaneous-convolutional-kernels-on-focal-plane-sensor-processors-2101.087152021-01-22 https://scifaro.com/en/abs/enabling-large-neural-networks-on-tiny-microcontrollers-with-swapping-2101.087442021-09-02 https://scifaro.com/en/abs/virtual-memory-partitioning-for-enhancing-application-performance-in-mobile-platforms-2101.088772021-01-25 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https://scifaro.com/en/abs/ironman-gnn-assisted-design-space-exploration-in-high-level-synthesis-via-reinforcement-learning-2102.081382021-12-10 https://scifaro.com/en/abs/toward-taming-the-overhead-monster-for-data-flow-integrity-2102.100312021-11-30 https://scifaro.com/en/abs/dither-computing-a-hybrid-deterministic-stochastic-computing-framework-2102.107322021-11-30 https://scifaro.com/en/abs/on-value-recomputation-to-accelerate-invisible-speculation-2102.109322021-12-06 https://scifaro.com/en/abs/silent-data-corruptions-at-scale-2102.112452021-02-23 https://scifaro.com/en/abs/cbp-coordinated-management-of-cache-partitioning-bandwidth-partitioning-and-prefetch-throttling-2102.115282021-02-24 https://scifaro.com/en/abs/fixar-a-fixed-point-deep-reinforcement-learning-platform-with-quantization-aware-training-and-adaptive-parallelism-2102.121032021-02-25 https://scifaro.com/en/abs/q-vr-system-level-design-for-future-mobile-collaborative-virtual-reality-2102.131912021-03-01 https://scifaro.com/en/abs/slap-a-split-latency-adaptive-vliw-pipeline-architecture-which-enables-on-the-fly-variable-simd-vector-length-2102.133012021-03-01 https://scifaro.com/en/abs/a-variable-vector-length-simd-architecture-for-hw-sw-co-designed-processors-2102.134102021-03-01 https://scifaro.com/en/abs/an-architecture-for-memory-centric-active-storage-mcas-2103.000072021-05-25 https://scifaro.com/en/abs/hir-an-mlir-based-intermediate-representation-for-hardware-accelerator-description-2103.001942021-03-02 https://scifaro.com/en/abs/problp-a-framework-for-low-precision-probabilistic-inference-2103.002162021-03-02 https://scifaro.com/en/abs/acceleration-of-probabilistic-reasoning-through-custom-processor-architecture-2103.002662021-03-02 https://scifaro.com/en/abs/sparkxd-a-framework-for-resilient-and-energy-efficient-spiking-neural-network-inference-using-approximate-dram-2103.004212023-03-06 https://scifaro.com/en/abs/mitigating-edge-machine-learning-inference-bottlenecks-an-empirical-study-on-accelerating-google-edge-models-2103.007682021-03-02 https://scifaro.com/en/abs/polynesia-enabling-effective-hybrid-transactional-analytical-databases-with-specialized-hardware-software-co-design-2103.007982021-03-02 https://scifaro.com/en/abs/layering-the-monitoring-action-for-improved-flexibility-and-overhead-control-work-in-progress-2103.011762021-03-02 https://scifaro.com/en/abs/run-time-performance-monitoring-of-heterogenous-hw-sw-platforms-using-papi-2103.011952021-03-02 https://scifaro.com/en/abs/sme-reram-based-sparse-multiplication-engine-to-squeeze-out-bit-sparsity-of-neural-network-2103.017052021-03-03 https://scifaro.com/en/abs/hardware-acceleration-of-fully-quantized-bert-for-efficient-natural-language-processing-2103.028002021-03-05 https://scifaro.com/en/abs/the-multi-dataflow-composer-tool-an-open-source-tool-suite-for-optimized-coarse-grain-reconfigurable-hardware-accelerators-and-platform-design-2103.035642021-03-08 https://scifaro.com/en/abs/reconfigurable-and-approximate-computing-for-video-coding-2103.037122021-03-08 https://scifaro.com/en/abs/odin-a-bit-parallel-stochastic-arithmetic-based-accelerator-for-in-situ-neural-network-processing-in-phase-change-ram-2103.039532021-03-09 https://scifaro.com/en/abs/comparative-analysis-and-enhancement-of-cfg-based-hardware-assisted-cfi-schemes-2103.044562021-03-09 https://scifaro.com/en/abs/scaling-up-hbm-efficiency-of-top-k-spmv-for-approximate-embedding-similarity-on-fpgas-2103.048082021-03-09 https://scifaro.com/en/abs/reliability-aware-quantization-for-anti-aging-npus-2103.048122022-03-16 https://scifaro.com/en/abs/f-cad-a-framework-to-explore-hardware-accelerators-for-codec-avatar-decoding-2103.049582021-03-09 https://scifaro.com/en/abs/representing-gate-level-set-faults-by-multiple-seu-faults-at-rtl-2103.051062021-03-10 https://scifaro.com/en/abs/eternal-thing-2-0-analog-trojan-resilient-ripple-less-solar-energy-harvesting-system-for-sustainable-iot-in-smart-cities-and-smart-villages-2103.056152021-03-10 https://scifaro.com/en/abs/mpu-towards-bandwidth-abundant-simt-processor-via-near-bank-computing-2103.066532021-03-12 https://scifaro.com/en/abs/exploring-the-mysteries-of-system-level-test-2103.066562021-03-12 https://scifaro.com/en/abs/design-principles-for-packet-deparsers-on-fpgas-2103.077502021-03-16 https://scifaro.com/en/abs/the-spinnaker-2-processing-element-architecture-for-hybrid-digital-neuromorphic-computing-2103.083922022-08-16 https://scifaro.com/en/abs/an-asic-implementation-and-evaluation-of-a-profiled-low-energy-instruction-set-architecture-extension-2103.089102021-03-17 https://scifaro.com/en/abs/softermax-hardware-software-co-design-of-an-efficient-softmax-for-transformers-2103.093012021-03-18 https://scifaro.com/en/abs/an-overflow-underflow-free-fixed-point-bit-width-optimization-method-for-os-elm-digital-circuit-2103.097912022-03-14 https://scifaro.com/en/abs/solving-large-top-k-graph-eigenproblems-with-a-memory-and-compute-optimized-fpga-design-2103.100402021-03-19 https://scifaro.com/en/abs/characterizing-the-communication-requirements-of-gnn-accelerators-a-model-based-approach-2103.105152021-03-22 https://scifaro.com/en/abs/gnnerator-a-hardware-software-framework-for-accelerating-graph-neural-networks-2103.108362021-03-22 https://scifaro.com/en/abs/special-session-reliability-analysis-for-ml-ai-hardware-2103.121662021-03-31 https://scifaro.com/en/abs/risc-nn-use-risc-not-cisc-as-neural-network-hardware-infrastructure-2103.123932021-03-24 https://scifaro.com/en/abs/de-specializing-an-hls-library-for-deep-neural-networks-improvements-upon-hls4ml-2103.130602021-03-25 https://scifaro.com/en/abs/reducing-load-latency-with-cache-level-prediction-2103.148082021-03-30 https://scifaro.com/en/abs/a-first-look-at-risc-v-virtualization-from-an-embedded-systems-perspective-2103.149512021-08-17 https://scifaro.com/en/abs/enabling-design-methodologies-and-future-trends-for-edge-ai-specialization-and-co-design-2103.157502021-03-31 https://scifaro.com/en/abs/gnetdet-object-detection-optimized-on-a-224mw-cnn-accelerator-chip-at-the-speed-of-106fps-2103.157562021-03-30 https://scifaro.com/en/abs/demonstrating-analog-inference-on-the-brainscales-2-mobile-system-2103.159602025-07-02 https://scifaro.com/en/abs/ewake-a-novel-architecture-for-semi-active-wake-up-radios-attaining-ultra-high-sensitivity-at-extremely-low-consumption-2103.159692021-03-31 https://scifaro.com/en/abs/an-energy-efficient-quad-camera-visual-system-for-autonomous-machines-on-fpga-platform-2104.001922021-04-02 https://scifaro.com/en/abs/compiler-infrastructure-for-specializing-domain-specific-memory-templates-2104.014482021-04-06 https://scifaro.com/en/abs/a-configurable-bnn-asic-using-a-network-of-programmable-threshold-logic-standard-cells-2104.016992021-04-06 https://scifaro.com/en/abs/modeling-gate-level-abstraction-hierarchy-using-graph-convolutional-neural-networks-to-predict-functional-de-rating-factors-2104.018122021-04-06 https://scifaro.com/en/abs/the-validation-of-graph-model-based-gate-level-low-dimensional-feature-data-for-machine-learning-applications-2104.019002021-04-06 https://scifaro.com/en/abs/composing-graph-theory-and-deep-neural-networks-to-evaluate-seu-type-soft-error-effects-2104.019082021-04-06 https://scifaro.com/en/abs/near-precise-parameter-approximation-for-multiple-multiplications-on-a-single-dsp-block-2104.021622021-10-26 https://scifaro.com/en/abs/gpu-domain-specialization-via-composable-on-package-architecture-2104.021882021-04-07 https://scifaro.com/en/abs/designing-efficient-and-high-performance-ai-accelerators-with-customized-stt-mram-2104.021992021-04-07 https://scifaro.com/en/abs/being-ahead-benchmarking-and-exploring-accelerators-for-hardware-efficient-ai-deployment-2104.022512021-04-07 https://scifaro.com/en/abs/building-beyond-hls-graph-analysis-and-others-2104.026762021-04-07 https://scifaro.com/en/abs/polynomial-circuit-verification-using-bdds-2104.030242021-04-08 https://scifaro.com/en/abs/a-matrix-math-facility-for-power-isa-tm-processors-2104.031422021-04-08 https://scifaro.com/en/abs/on-fpga-training-with-ultra-memory-reduction-a-low-precision-tensor-method-2104.034202021-04-21 https://scifaro.com/en/abs/enabling-cross-domain-communication-how-to-bridge-the-gap-between-ai-and-hw-engineers-2104.037802021-04-12 https://scifaro.com/en/abs/algorithmic-obfuscation-for-ldpc-decoders-2104.038142022-11-04 https://scifaro.com/en/abs/autosva-democratizing-formal-verification-of-rtl-module-interactions-2104.040032021-04-12 https://scifaro.com/en/abs/fixed-posit-a-floating-point-representation-for-error-resilient-applications-2104.047632021-04-13 https://scifaro.com/en/abs/ielas-an-elas-based-energy-efficient-accelerator-for-real-time-stereo-matching-on-fpga-platform-2104.051122021-04-13 https://scifaro.com/en/abs/burstlink-techniques-for-energy-efficient-conventional-and-virtual-reality-video-display-2104.051192021-11-03 https://scifaro.com/en/abs/npe-an-fpga-based-overlay-processor-for-natural-language-processing-2104.065352021-04-15 https://scifaro.com/en/abs/sisa-set-centric-instruction-set-architecture-for-graph-mining-on-processing-in-memory-systems-2104.075822021-10-26 https://scifaro.com/en/abs/pluto-enabling-massively-parallel-computation-in-dram-via-lookup-tables-2104.076992025-01-24 https://scifaro.com/en/abs/performance-analysis-and-optimization-opportunities-for-nvidia-automotive-gpus-2104.077352021-04-19 https://scifaro.com/en/abs/demystifying-memory-access-patterns-of-fpga-based-graph-processing-accelerators-2104.077762021-04-19 https://scifaro.com/en/abs/a-survey-on-dependable-digital-systems-using-fpgas-current-methods-and-challenges-2104.083332021-04-20 https://scifaro.com/en/abs/demystifying-bert-implications-for-accelerator-design-2104.083352021-04-20 https://scifaro.com/en/abs/fox-hardware-assisted-file-auditing-for-direct-access-nvm-hosted-filesystems-2104.086992021-04-22 https://scifaro.com/en/abs/barrier-free-large-scale-sparse-tensor-accelerator-barista-for-convolutional-neural-networks-2104.087342021-05-11 https://scifaro.com/en/abs/codeapeel-an-integrated-and-layered-learning-technology-for-computer-architecture-courses-2104.095022021-11-30 https://scifaro.com/en/abs/reducing-solid-state-drive-read-latency-by-optimizing-read-retry-2104.096112021-04-21 https://scifaro.com/en/abs/sme-a-high-productivity-fpga-tool-for-software-programmers-2104.097682021-04-21 https://scifaro.com/en/abs/codr-computation-and-data-reuse-aware-cnn-accelerator-2104.097982021-04-21 https://scifaro.com/en/abs/tackling-variabilities-in-autonomous-driving-2104.104152021-04-22 https://scifaro.com/en/abs/neuromorphic-algorithm-hardware-codesign-for-temporal-pattern-learning-2104.107122021-05-10 https://scifaro.com/en/abs/enabling-cross-layer-reliability-and-functional-safety-assessment-through-ml-based-compact-models-2104.109412021-04-23 https://scifaro.com/en/abs/a-case-for-fine-grain-coherence-specialization-in-heterogeneous-systems-2104.116782021-04-26 https://scifaro.com/en/abs/tensorlib-a-spatial-accelerator-generation-framework-for-tensor-algebra-2104.123392021-04-27 https://scifaro.com/en/abs/capstan-a-vector-rda-for-sparsity-2104.127602021-09-24 https://scifaro.com/en/abs/continual-learning-approach-for-improving-the-data-and-computation-mapping-in-near-memory-processing-system-2104.136712021-04-29 https://scifaro.com/en/abs/magma-an-optimization-framework-for-mapping-multiple-dnns-on-multiple-accelerator-cores-2104.139972022-01-28 https://scifaro.com/en/abs/automated-design-space-exploration-of-cgra-processing-element-architectures-using-frequent-subgraph-analysis-2104.141552021-04-30 https://scifaro.com/en/abs/hardware-implementation-of-an-opc-ua-server-for-industrial-field-devices-2105.007892021-11-23 https://scifaro.com/en/abs/hasco-towards-agile-hardware-and-software-co-design-for-tensor-computation-2105.015852021-05-05 https://scifaro.com/en/abs/tenet-a-framework-for-modeling-tensor-dataflow-based-on-relation-centric-notation-2105.018922021-05-06 https://scifaro.com/en/abs/coherence-attacks-and-countermeasures-in-interposer-based-systems-2105.029172022-01-10 https://scifaro.com/en/abs/damov-a-new-methodology-and-benchmark-suite-for-evaluating-data-movement-bottlenecks-2105.037252023-04-07 https://scifaro.com/en/abs/benchmarking-a-new-paradigm-an-experimental-analysis-of-a-real-processing-in-memory-architecture-2105.038142022-05-06 https://scifaro.com/en/abs/rrcd-redirecci-on-de-registros-basada-en-compresi-on-de-datos-para-tolerar-fallospermanentes-en-una-gpu-2105.038592021-05-11 https://scifaro.com/en/abs/skew-oblivious-data-routing-for-data-intensive-applications-on-fpgas-with-hls-2105.041512021-05-11 https://scifaro.com/en/abs/efficient-error-correcting-code-mechanism-for-high-throughput-memristive-processing-in-memory-2105.042122021-05-11 https://scifaro.com/en/abs/on-the-approximation-of-accuracy-configurable-sequential-multipliers-via-segmented-carry-chains-2105.055882021-05-26 https://scifaro.com/en/abs/simnet-accurate-and-high-performance-computer-architecture-simulation-using-deep-learning-2105.058212022-04-07 https://scifaro.com/en/abs/combining-emulation-and-simulation-to-evaluate-a-near-memory-key-value-lookup-accelerator-2105.065942021-05-17 https://scifaro.com/en/abs/hardware-synthesis-of-state-space-equations-application-to-fpga-implementation-of-shallow-and-deep-neural-networks-2105.071312021-05-18 https://scifaro.com/en/abs/zero-aware-configurable-data-encoding-by-skipping-transfer-for-error-resilient-applications-2105.074322021-05-18 https://scifaro.com/en/abs/multi-output-multi-level-multi-gate-design-using-non-linear-programming-2105.077842021-05-18 https://scifaro.com/en/abs/metasys-a-practical-open-source-metadata-management-system-to-implement-and-evaluate-cross-layer-optimizations-2105.081232023-01-24 https://scifaro.com/en/abs/impulse-a-65nm-digital-compute-in-memory-macro-with-fused-weights-and-membrane-potential-for-spike-based-sequential-learning-tasks-2105.082172021-07-09 https://scifaro.com/en/abs/a-new-computationally-efficient-blech-criterion-for-immortality-in-general-interconnects-2105.087842021-05-20 https://scifaro.com/en/abs/recpipe-co-designing-models-and-hardware-to-jointly-optimize-recommendation-quality-and-performance-2105.088202021-05-25 https://scifaro.com/en/abs/block-convolution-towards-memory-efficient-inference-of-large-scale-cnns-on-fpga-2105.089372021-05-20 https://scifaro.com/en/abs/quac-trng-high-throughput-true-random-number-generation-using-quadruple-row-activation-in-commodity-dram-chips-2105.089552021-05-26 https://scifaro.com/en/abs/high-performance-fpga-based-accelerator-for-bayesian-neural-networks-2105.091632021-12-02 https://scifaro.com/en/abs/learning-pareto-frontier-resource-management-policies-for-heterogeneous-socs-an-information-theoretic-approach-2105.092822021-05-20 https://scifaro.com/en/abs/dual-side-sparse-tensor-core-2105.095642021-05-21 https://scifaro.com/en/abs/optimizing-the-use-of-behavioral-locking-for-high-level-synthesis-2105.096662022-06-08 https://scifaro.com/en/abs/a-terabit-hybrid-fpga-asic-platform-for-switch-virtualization-2105.096962021-05-21 https://scifaro.com/en/abs/prefetcher-based-dram-architecture-2105.104272021-05-24 https://scifaro.com/en/abs/gnnie-gnn-inference-engine-with-load-balancing-and-graph-specific-caching-2105.105542021-08-10 https://scifaro.com/en/abs/27-5-29-5-ghz-switched-array-sounder-for-dynamic-channel-characterization-design-implementation-and-measurements-2105.107122021-05-25 https://scifaro.com/en/abs/scalabfs-a-scalable-bfs-accelerator-on-hbm-enhanced-fpgas-2105.117542021-10-13 https://scifaro.com/en/abs/atria-a-bit-parallel-stochastic-arithmetic-based-accelerator-for-in-dram-cnn-processing-2105.127812021-05-28 https://scifaro.com/en/abs/simdram-an-end-to-end-framework-for-bit-serial-simd-computing-in-dram-2105.128392021-07-01 https://scifaro.com/en/abs/compiling-halide-programs-to-push-memory-accelerators-2105.128582021-05-28 https://scifaro.com/en/abs/a-microarchitecture-implementation-framework-for-online-learning-with-temporal-neural-networks-2105.132622021-11-09 https://scifaro.com/en/abs/fuseconv-fully-separable-convolutions-for-fast-inference-on-systolic-arrays-2105.134342021-05-31 https://scifaro.com/en/abs/an-in-memory-analog-computing-co-processor-for-energy-efficient-cnn-inference-on-mobile-devices-2105.139042021-09-15 https://scifaro.com/en/abs/ecmo-peripheral-transplantation-to-rehost-embedded-linux-kernels-2105.142952021-10-06 https://scifaro.com/en/abs/a-tapered-floating-point-extension-for-the-redundant-signed-radix-2-system-using-the-canonical-recoding-2105.144012021-06-01 https://scifaro.com/en/abs/reuse-distance-based-copy-backs-of-clean-cache-lines-to-lower-level-caches-2105.144422021-06-01 https://scifaro.com/en/abs/how-flexible-is-your-computing-system-2106.011392021-06-03 https://scifaro.com/en/abs/dagger-accelerating-rpcs-in-cloud-microservices-through-tightly-coupled-reconfigurable-nics-2106.014822021-06-04 https://scifaro.com/en/abs/analyzing-crosstalk-error-in-the-nisq-era-2106.016712021-06-04 https://scifaro.com/en/abs/micro-btb-a-high-performance-and-lightweight-last-level-branch-target-buffer-for-servers-2106.042052021-07-06 https://scifaro.com/en/abs/hyca-a-hybrid-computing-architecture-for-fault-tolerant-deep-learning-2106.047722021-10-28 https://scifaro.com/en/abs/vector-symbolic-architectures-as-a-computing-framework-for-emerging-hardware-2106.052682023-07-21 https://scifaro.com/en/abs/codic-a-low-cost-substrate-for-enabling-custom-in-dram-functionalities-and-optimizations-2106.056322021-06-11 https://scifaro.com/en/abs/fpga-based-near-memory-acceleration-of-modern-data-intensive-applications-2106.064332021-07-06 https://scifaro.com/en/abs/ithing-designing-next-generation-things-with-battery-health-self-monitoring-capabilities-for-sustainable-iot-in-smart-cities-2106.066782021-06-15 https://scifaro.com/en/abs/koios-a-deep-learning-benchmark-suite-for-fpga-architecture-and-cad-research-2106.070872021-06-15 https://scifaro.com/en/abs/extending-the-risc-v-isa-for-exploring-advanced-reconfigurable-simd-instructions-2106.074562021-06-15 https://scifaro.com/en/abs/s2engine-a-novel-systolic-architecture-for-sparse-convolutional-neural-networks-2106.078942021-06-16 https://scifaro.com/en/abs/exploring-the-feasibility-of-using-3d-xpoint-as-an-in-memory-computing-accelerator-2106.084022021-06-17 https://scifaro.com/en/abs/forms-fine-grained-polarized-reram-based-in-situ-computation-for-mixed-signal-dnn-accelerator-2106.091442021-06-18 https://scifaro.com/en/abs/characterization-and-mitigation-of-electromigration-effects-in-tsv-based-power-delivery-network-enabled-3d-stacked-drams-2106.093082021-06-18 https://scifaro.com/en/abs/a-system-level-voltage-frequency-scaling-characterization-framework-for-multicore-cpus-2106.099752021-06-21 https://scifaro.com/en/abs/towards-accurate-performance-modeling-of-risc-v-designs-2106.099912021-06-21 https://scifaro.com/en/abs/effects-of-vlsi-circuit-constraints-on-temporal-coding-multilayer-spiking-neural-networks-2106.103822021-06-28 https://scifaro.com/en/abs/effective-pre-silicon-verification-of-processor-cores-by-breaking-the-bounds-of-symbolic-quick-error-detection-2106.103922021-07-01 https://scifaro.com/en/abs/content-addressable-parallel-processors-on-a-fpga-2106.113762021-06-25 https://scifaro.com/en/abs/a-construction-kit-for-efficient-low-power-neural-network-accelerator-designs-2106.128102021-06-25 https://scifaro.com/en/abs/occam-optimal-data-reuse-for-convolutional-neural-networks-2106.141382021-06-29 https://scifaro.com/en/abs/revamping-storage-class-memory-with-hardware-automated-memory-over-storage-solution-2106.142412021-06-29 https://scifaro.com/en/abs/half-holistic-auto-machine-learning-for-fpgas-2106.147712021-10-22 https://scifaro.com/en/abs/nmpo-near-memory-computing-profiling-and-offloading-2106.152842021-06-30 https://scifaro.com/en/abs/impact-of-on-chip-interconnect-on-in-memory-acceleration-of-deep-neural-networks-2107.023582021-07-07 https://scifaro.com/en/abs/cap-ram-a-charge-domain-in-memory-computing-6t-sram-for-accurate-and-precision-programmable-cnn-inference-2107.023882021-07-07 https://scifaro.com/en/abs/energy-efficient-accelerator-design-for-deformable-convolution-networks-2107.025472021-07-07 https://scifaro.com/en/abs/area-delay-efficeint-fpga-design-of-32-bit-euclid-s-gcd-based-on-sum-of-absolute-difference-2107.027622022-11-18 https://scifaro.com/en/abs/r2f-a-remote-retraining-framework-for-aiot-processors-with-computing-errors-2107.030962021-07-08 https://scifaro.com/en/abs/mafia-machine-learning-acceleration-on-fpgas-for-iot-applications-2107.036532021-07-09 https://scifaro.com/en/abs/first-generation-inference-accelerator-deployment-at-facebook-2107.041402021-08-06 https://scifaro.com/en/abs/winocnn-kernel-sharing-winograd-systolic-array-for-efficient-convolutional-neural-network-acceleration-on-fpgas-2107.042442021-07-12 https://scifaro.com/en/abs/neat-low-complexity-efficient-on-chip-cache-coherence-2107.054532021-07-27 https://scifaro.com/en/abs/uncertainty-modeling-of-emerging-device-based-computing-in-memory-neural-accelerators-with-application-to-neural-architecture-search-2107.068712021-07-15 https://scifaro.com/en/abs/arrow-a-risc-v-vector-accelerator-for-machine-learning-inference-2107.071692021-07-16 https://scifaro.com/en/abs/s2ta-exploiting-structured-sparsity-for-energy-efficient-mobile-cnn-acceleration-2107.079832022-01-07 https://scifaro.com/en/abs/zipper-exploiting-tile-and-operator-level-parallelism-for-general-and-scalable-graph-neural-network-acceleration-2107.087092021-07-20 https://scifaro.com/en/abs/accelerating-weather-prediction-using-near-memory-reconfigurable-fabric-2107.087162021-12-22 https://scifaro.com/en/abs/dynamic-lockstep-processors-for-applications-with-functional-safety-relevance-2107.089972021-07-20 https://scifaro.com/en/abs/compute-rams-adaptable-compute-and-storage-blocks-for-dl-optimized-fpgas-2107.091782021-10-01 https://scifaro.com/en/abs/revisiting-residue-codes-for-modern-memories-2107.092452022-12-20 https://scifaro.com/en/abs/streamblocks-a-compiler-for-heterogeneous-dataflow-computing-technical-report-2107.093332021-07-21 https://scifaro.com/en/abs/positive-negative-approximate-multipliers-for-dnn-accelerators-2107.093662022-03-17 https://scifaro.com/en/abs/crew-computation-reuse-and-efficient-weight-storage-for-hardware-accelerated-mlps-and-rnns-2107.094082022-03-14 https://scifaro.com/en/abs/dnn-is-not-all-you-need-parallelizing-non-neural-ml-algorithms-on-ultra-low-power-iot-processors-2107.094482022-11-15 https://scifaro.com/en/abs/domino-a-tailored-network-on-chip-architecture-to-enable-highly-localized-inter-and-intra-memory-dnn-computing-2107.095002021-07-21 https://scifaro.com/en/abs/the-bitlet-model-a-parameterized-analytical-model-to-compare-pim-and-cpu-systems-2107.103082021-07-23 https://scifaro.com/en/abs/architecting-optically-controlled-phase-change-memory-2107.115162021-07-27 https://scifaro.com/en/abs/lighton-optical-processing-unit-scaling-up-ai-and-hpc-with-a-non-von-neumann-co-processor-2107.118142022-12-28 https://scifaro.com/en/abs/ultra-fast-high-performance-8x8-approximate-multipliers-by-a-new-multicolumn-3-3-2-inexact-compressor-and-its-derivatives-2107.118812023-08-16 https://scifaro.com/en/abs/mfagan-a-compression-framework-for-memory-efficient-on-device-super-resolution-gan-2107.126792021-07-28 https://scifaro.com/en/abs/griffin-rethinking-sparse-optimization-for-deep-learning-architectures-2107.129222021-11-03 https://scifaro.com/en/abs/spots-an-accelerator-for-sparse-convolutional-networks-leveraging-systolic-general-matrix-matrix-multiplication-2107.133862021-11-29 https://scifaro.com/en/abs/reuse-cache-for-heterogeneous-cpu-gpu-systems-2107.136492021-07-30 https://scifaro.com/en/abs/communication-avoiding-micro-architecture-to-compute-xcorr-scores-for-peptide-identification-2108.001472021-10-15 https://scifaro.com/en/abs/an-efficient-reverse-lookup-table-based-strategy-for-solving-the-synonym-and-cache-coherence-problem-in-virtually-indexed-virtually-tagged-caches-2108.004442021-08-03 https://scifaro.com/en/abs/accelerating-markov-random-field-inference-with-uncertainty-quantification-2108.005702021-08-03 https://scifaro.com/en/abs/analysing-digital-in-memory-computing-for-advanced-finfet-node-2108.007782021-08-11 https://scifaro.com/en/abs/energy-efficiency-aspects-of-the-amd-zen-2-architecture-2108.008082021-10-26 https://scifaro.com/en/abs/rfc-hypgcn-a-runtime-sparse-feature-compress-accelerator-for-skeleton-based-gcns-action-recognition-model-with-hybrid-pruning-2108.010202021-08-03 https://scifaro.com/en/abs/synthesizing-brain-network-inspired-interconnections-for-large-scale-network-on-chips-2108.012982021-08-30 https://scifaro.com/en/abs/hardware-aware-design-of-multiplierless-second-order-iir-filters-with-minimum-adders-2108.015652022-05-11 https://scifaro.com/en/abs/efficient-hardware-realizations-of-feedforward-artificial-neural-networks-2108.020732021-08-05 https://scifaro.com/en/abs/spartus-a-9-4-top-s-fpga-based-lstm-accelerator-exploiting-spatio-temporal-sparsity-2108.022972022-06-14 https://scifaro.com/en/abs/beanna-a-binary-enabled-architecture-for-neural-network-acceleration-2108.023132021-08-06 https://scifaro.com/en/abs/verlpy-python-library-for-verification-of-digital-designs-with-reinforcement-learning-2108.039782021-08-10 https://scifaro.com/en/abs/understanding-tool-synthesis-behavior-and-safe-finite-state-machine-design-2108.040422021-08-10 https://scifaro.com/en/abs/taming-process-variations-in-cnfet-for-efficient-last-level-cache-design-2108.050232021-08-12 https://scifaro.com/en/abs/testable-designs-of-toffoli-fredkin-reversible-circuits-2108.074482021-08-24 https://scifaro.com/en/abs/edge-ai-without-compromise-efficient-versatile-and-accurate-neurocomputing-in-resistive-random-access-memory-2108.078792021-08-19 https://scifaro.com/en/abs/monarch-a-durable-polymorphic-memory-for-data-intensive-applications-2108.084972021-08-20 https://scifaro.com/en/abs/programmable-fpga-based-memory-controller-2108.096012021-08-24 https://scifaro.com/en/abs/respawn-energy-efficient-fault-tolerance-for-spiking-neural-networks-considering-unreliable-memories-2108.102712023-03-06 https://scifaro.com/en/abs/metro-a-software-hardware-co-design-of-interconnections-for-spatial-dnn-accelerators-2108.105702025-02-19 https://scifaro.com/en/abs/design-and-scaffolded-training-of-an-efficient-dnn-operator-for-computer-vision-on-the-edge-2108.114412021-08-27 https://scifaro.com/en/abs/efficient-on-chip-communication-for-parallel-graph-analytics-on-spatial-architectures-2108.115212022-09-07 https://scifaro.com/en/abs/synthesis-of-predictable-global-noc-by-abutment-in-synchoros-vlsi-design-2108.122132021-08-30 https://scifaro.com/en/abs/terabit-per-second-multicore-polar-code-successive-cancellation-decoders-2108.122922021-08-30 https://scifaro.com/en/abs/actres-analog-clock-tree-synthesis-2108.128972021-08-31 https://scifaro.com/en/abs/multpim-fast-stateful-multiplication-for-processing-in-memory-2108.133782021-09-21 https://scifaro.com/en/abs/agon-a-scalable-competitive-scheduler-for-large-heterogeneous-systems-2109.006652021-09-03 https://scifaro.com/en/abs/a-novel-compaction-approach-for-sbst-test-programs-2109.009582021-09-09 https://scifaro.com/en/abs/an-electro-photonic-system-for-accelerating-deep-neural-networks-2109.011262023-09-20 https://scifaro.com/en/abs/on-the-accuracy-of-analog-neural-network-inference-accelerators-2109.012622023-02-03 https://scifaro.com/en/abs/smart-a-heterogeneous-scratchpad-memory-architecture-for-superconductor-sfq-based-systolic-cnn-accelerators-2109.012692021-09-06 https://scifaro.com/en/abs/end-to-end-100-tops-w-inference-with-analog-in-memory-computing-are-we-there-yet-2109.014042021-09-06 https://scifaro.com/en/abs/limited-associativity-makes-concurrent-software-caches-a-breeze-2109.030212021-09-08 https://scifaro.com/en/abs/augmented-memory-computing-dynamically-augmented-sram-storage-for-data-intensive-applications-2109.030222021-09-08 https://scifaro.com/en/abs/versa-a-dataflow-centric-multiprocessor-with-36-systolic-arm-cortex-m4f-cores-and-a-reconfigurable-crossbar-memory-hierarchy-in-28nm-2109.030242021-09-09 https://scifaro.com/en/abs/high-resolution-waveform-capture-device-on-a-cyclone-v-fpga-2109.030262021-09-08 https://scifaro.com/en/abs/only-six-passive-circuit-elements-are-existent-2109.030412021-10-08 https://scifaro.com/en/abs/efficient-instruction-scheduling-using-real-time-load-delay-tracking-2109.031122021-09-08 https://scifaro.com/en/abs/iceclave-a-trusted-execution-environment-for-in-storage-computing-2109.033732021-09-09 https://scifaro.com/en/abs/resistive-neural-hardware-accelerators-2109.039342021-09-10 https://scifaro.com/en/abs/a-fast-and-effective-early-stage-multi-level-cache-optimization-method-based-on-reuse-distance-analysis-2109.046142021-09-13 https://scifaro.com/en/abs/ohm-gpu-integrating-new-optical-network-and-heterogeneous-memory-into-gpu-multi-processors-2109.054302021-09-14 https://scifaro.com/en/abs/data-centric-and-data-aware-frameworks-for-fundamentally-efficient-data-handling-in-modern-computing-systems-2109.058812021-09-14 https://scifaro.com/en/abs/optimizing-fpga-based-accelerator-design-for-large-scale-molecular-similarity-search-2109.063552021-09-15 https://scifaro.com/en/abs/cohmeleon-learning-based-orchestration-of-accelerator-coherence-in-heterogeneous-socs-2109.063822021-09-15 https://scifaro.com/en/abs/dataflow-accelerator-architecture-for-autonomous-machine-computing-2109.070472022-06-24 https://scifaro.com/en/abs/union-a-unified-hw-sw-co-design-ecosystem-in-mlir-for-evaluating-tensor-operations-on-spatial-accelerators-2109.074192021-11-09 https://scifaro.com/en/abs/the-accuracy-and-efficiency-of-posit-arithmetic-2109.082252021-09-20 https://scifaro.com/en/abs/reconfigurable-low-latency-memory-system-for-sparse-matricized-tensor-times-khatri-rao-product-on-fpga-2109.088742021-09-21 https://scifaro.com/en/abs/ai-accelerator-survey-and-trends-2109.089572021-12-13 https://scifaro.com/en/abs/g-cos-gnn-accelerator-co-search-towards-both-better-accuracy-and-efficiency-2109.089832021-09-21 https://scifaro.com/en/abs/making-memristive-processing-in-memory-reliable-2109.096872021-09-21 https://scifaro.com/en/abs/das-dynamic-adaptive-scheduling-for-energy-efficient-heterogeneous-socs-2109.110692021-09-24 https://scifaro.com/en/abs/gpu4s-embedded-gpus-in-space-latest-project-updates-2109.110742021-09-24 https://scifaro.com/en/abs/sextans-a-streaming-accelerator-for-general-purpose-sparse-matrix-dense-matrix-multiplication-2109.110812022-01-14 https://scifaro.com/en/abs/pythia-a-customizable-hardware-prefetching-framework-using-online-reinforcement-learning-2109.120212023-04-07 https://scifaro.com/en/abs/comet-an-integrated-interval-thermal-simulation-toolchain-for-2d-2-5d-and-3d-processor-memory-systems-2109.124052022-03-18 https://scifaro.com/en/abs/harp-practically-and-effectively-identifying-uncorrectable-errors-in-memory-chips-that-use-on-die-error-correcting-codes-2109.126972021-12-21 https://scifaro.com/en/abs/google-neural-network-models-for-edge-devices-analyzing-and-mitigating-machine-learning-inference-bottlenecks-2109.143202021-09-30 https://scifaro.com/en/abs/improving-dram-performance-security-and-reliability-by-understanding-and-exploiting-dram-timing-parameter-margins-2109.145202021-09-30 https://scifaro.com/en/abs/secda-efficient-hardware-software-co-design-of-fpga-based-dnn-accelerators-for-edge-inference-2110.004782021-10-04 https://scifaro.com/en/abs/heterogeneous-dual-core-overlay-processor-for-light-weight-cnns-2110.011032021-10-05 https://scifaro.com/en/abs/hygain-high-performance-energy-efficient-hybrid-gain-cell-based-cache-hierarchy-2110.012082021-10-07 https://scifaro.com/en/abs/benchmarking-memory-centric-computing-systems-analysis-of-real-processing-in-memory-hardware-2110.017092023-04-04 https://scifaro.com/en/abs/rasa-efficient-register-aware-systolic-array-matrix-engine-for-cpu-2110.017522021-10-06 https://scifaro.com/en/abs/shift-bnn-highly-efficient-probabilistic-bayesian-neural-network-training-via-memory-friendly-pattern-retrieving-2110.035532021-10-08 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https://scifaro.com/en/abs/unveiling-the-real-performance-of-lpddr5-memories-2209.147562022-10-03 https://scifaro.com/en/abs/real-time-scheduling-of-machine-learning-operations-on-heterogeneous-neuromorphic-soc-2209.147772022-09-30 https://scifaro.com/en/abs/approximate-computing-and-the-efficient-machine-learning-expedition-2210.004972022-10-04 https://scifaro.com/en/abs/risc-v-toolchain-and-agile-development-based-open-source-neuromorphic-processor-2210.005622022-10-07 https://scifaro.com/en/abs/safesoftdr-a-library-to-enable-software-based-diverse-redundancy-for-safety-critical-tasks-2210.008332022-10-04 https://scifaro.com/en/abs/towards-the-multiple-constant-multiplication-at-minimal-hardware-cost-2210.027422022-10-11 https://scifaro.com/en/abs/pef-poisson-s-equation-based-large-scale-fixed-outline-floorplanning-2210.032932022-10-10 https://scifaro.com/en/abs/efficient-computation-of-map-scale-continuous-mutual-information-on-chip-in-real-time-2210.036232022-10-10 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https://scifaro.com/en/abs/a-low-power-1-gb-s-line-driver-with-configurable-pre-emphasis-for-lossy-transmission-lines-2210.118822023-04-26 https://scifaro.com/en/abs/an-analytical-estimation-of-spiking-neural-networks-energy-efficiency-2210.131072023-04-17 https://scifaro.com/en/abs/dpu-v2-energy-efficient-execution-of-irregular-directed-acyclic-graphs-2210.131842022-10-25 https://scifaro.com/en/abs/nasa-neural-architecture-search-and-acceleration-for-hardware-inspired-hybrid-networks-2210.133612022-12-20 https://scifaro.com/en/abs/the-championship-simulator-architectural-simulation-for-education-and-competition-2210.143242022-10-27 https://scifaro.com/en/abs/multi-objective-hardware-mapping-co-optimisation-for-multi-dnn-workloads-on-chiplet-based-accelerators-2210.146572024-08-26 https://scifaro.com/en/abs/deepfake-cli-accelerated-deepfake-detection-using-fpgas-2210.147432022-10-27 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https://scifaro.com/en/abs/mes-attacks-software-controlled-covert-channels-based-on-mutual-exclusion-and-synchronization-2211.118552022-11-23 https://scifaro.com/en/abs/the-amd-rome-memory-barrier-2211.118672022-11-23 https://scifaro.com/en/abs/design-and-performance-analysis-of-hardware-realization-of-3gpp-physical-layer-for-5g-cell-search-2211.120722022-11-23 https://scifaro.com/en/abs/utopia-fast-and-efficient-address-translation-via-hybrid-restrictive-flexible-virtual-to-physical-address-mappings-2211.122052023-10-09 https://scifaro.com/en/abs/arrayflex-a-systolic-array-architecture-with-configurable-transparent-pipelining-2211.126002023-06-07 https://scifaro.com/en/abs/micro-architectural-features-as-soft-error-induced-fault-executions-markers-in-embedded-safety-critical-systems-a-preliminary-study-2211.130102023-08-31 https://scifaro.com/en/abs/characterizing-a-neutron-induced-fault-model-for-deep-neural-networks-2211.130942022-11-24 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https://scifaro.com/en/abs/aocstream-all-on-chip-cnn-accelerator-with-stream-based-line-buffer-architecture-2212.114382022-12-23 https://scifaro.com/en/abs/fado-floorplan-aware-directive-optimization-for-high-level-synthesis-designs-on-multi-die-fpgas-2212.115822023-02-07 https://scifaro.com/en/abs/approximate-scan-flip-flop-to-reduce-functional-path-delay-and-power-consumption-2212.123602022-12-26 https://scifaro.com/en/abs/thermal-heating-in-reram-crossbar-arrays-challenges-and-solutions-2212.137072023-02-02 https://scifaro.com/en/abs/tensorfhe-achieving-practical-computation-on-encrypted-data-using-gpgpu-2212.141912023-01-02 https://scifaro.com/en/abs/barvinn-arbitrary-precision-dnn-accelerator-controlled-by-a-risc-v-cpu-2301.002902023-01-03 https://scifaro.com/en/abs/daemon-architectural-support-for-efficient-data-movement-in-disaggregated-systems-2301.004142023-01-20 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https://scifaro.com/en/abs/revet-a-language-and-compiler-for-dataflow-threads-2302.061242024-02-01 https://scifaro.com/en/abs/an-optical-xnor-bitcount-based-accelerator-for-efficient-inference-of-binary-neural-networks-2302.064052023-03-21 https://scifaro.com/en/abs/analog-in-memory-compute-architectures-for-artificial-intelligence-2302.064172023-02-14 https://scifaro.com/en/abs/an-818-tops-w-csnr-31db-sqnr-45db-10-bit-capacitor-reconfiguring-computing-in-memory-macro-with-software-analog-co-design-for-transformers-2302.064632023-02-14 https://scifaro.com/en/abs/openhls-high-level-synthesis-for-low-latency-deep-neural-networks-for-experimental-science-2302.067512023-03-17 https://scifaro.com/en/abs/sconna-a-stochastic-computing-based-optical-accelerator-for-ultra-fast-energy-efficient-inference-of-integer-quantized-cnns-2302.070362023-02-15 https://scifaro.com/en/abs/asmcap-an-approximate-string-matching-accelerator-for-genome-sequence-analysis-based-on-capacitive-content-addressable-memory-2302.074782023-02-16 https://scifaro.com/en/abs/redas-a-lightweight-architecture-for-supporting-fine-grained-reshaping-and-multiple-dataflows-on-systolic-array-2302.075202024-05-16 https://scifaro.com/en/abs/agni-in-situ-iso-latency-stochastic-to-binary-number-conversion-for-in-dram-deep-learning-2302.077462023-02-16 https://scifaro.com/en/abs/colibries-a-milliwatts-risc-v-based-embedded-system-leveraging-neuromorphic-and-neural-networks-hardware-accelerators-for-low-latency-closed-loop-control-applications-2302.079572023-02-17 https://scifaro.com/en/abs/cxl-over-ethernet-a-novel-fpga-based-memory-disaggregation-design-in-data-centers-2302.080552023-02-23 https://scifaro.com/en/abs/an-implementation-of-a-dual-processor-system-on-fpga-2302.083222023-05-23 https://scifaro.com/en/abs/a-bit-parallel-deterministic-stochastic-multiplier-2302.083242023-02-17 https://scifaro.com/en/abs/vegeta-vertically-integrated-extensions-for-sparse-dense-gemm-tile-acceleration-on-cpus-2302.086872023-02-24 https://scifaro.com/en/abs/vita-a-vision-transformer-inference-accelerator-for-edge-applications-2302.091082023-09-13 https://scifaro.com/en/abs/reducing-the-memory-usage-of-lattice-boltzmann-schemes-with-a-dwt-based-compression-2302.098832023-02-21 https://scifaro.com/en/abs/ata-cache-contention-mitigation-for-gpu-shared-l1-cache-with-aggregated-tag-array-2302.106382023-02-22 https://scifaro.com/en/abs/dynamic-resource-partitioning-for-multi-tenant-systolic-array-based-dnn-accelerator-2302.108062023-02-22 https://scifaro.com/en/abs/mp-rec-hardware-software-co-design-to-enable-multi-path-recommendation-2302.108722023-02-22 https://scifaro.com/en/abs/hlsdataset-open-source-dataset-for-ml-assisted-fpga-design-using-high-level-synthesis-2302.109772023-08-22 https://scifaro.com/en/abs/monad-towards-cost-effective-specialization-for-chiplet-based-spatial-accelerators-2302.112562024-04-16 https://scifaro.com/en/abs/from-circuits-to-soc-processors-arithmetic-approximation-techniques-embedded-computing-methodologies-for-dsp-acceleration-2302.121942024-09-09 https://scifaro.com/en/abs/sequence-based-incremental-concolic-testing-of-rtl-models-2302.122412024-04-18 https://scifaro.com/en/abs/a-chisel-framework-for-flexible-design-space-exploration-through-a-functional-approach-2302.127022023-02-27 https://scifaro.com/en/abs/machine-learning-based-low-overhead-congestion-control-algorithm-for-industrial-nocs-2302.127792023-02-27 https://scifaro.com/en/abs/asynchronous-persistence-with-asap-2302.133942023-02-28 https://scifaro.com/en/abs/at-scale-evaluation-of-weight-clustering-to-enable-energy-efficient-object-detection-2302.144262023-03-01 https://scifaro.com/en/abs/acceltran-a-sparsity-aware-accelerator-for-dynamic-inference-with-transformers-2302.147052023-05-02 https://scifaro.com/en/abs/tiny-classifier-circuits-evolving-accelerators-for-tabular-data-2303.000312023-09-29 https://scifaro.com/en/abs/bp-ntt-fast-and-compact-in-sram-number-theoretic-transform-with-bit-parallel-modular-multiplication-2303.001732023-04-25 https://scifaro.com/en/abs/q2logic-an-coarse-grained-architecture-targeting-schr-odinger-quantum-circuit-simulations-2303.016062023-03-06 https://scifaro.com/en/abs/unsupervised-recycled-fpga-detection-using-symmetry-analysis-2303.018072023-03-06 https://scifaro.com/en/abs/holistic-ijtag-based-external-and-internal-fault-monitoring-in-uavs-2303.018162023-03-06 https://scifaro.com/en/abs/automating-constraint-aware-datapath-optimization-using-e-graphs-2303.018392023-03-06 https://scifaro.com/en/abs/parentt-low-latency-parallel-residue-number-system-and-ntt-based-long-polynomial-modular-multiplication-for-homomorphic-encryption-2303.022372024-03-21 https://scifaro.com/en/abs/satin-hardware-for-boolean-satisfiability-inference-2303.025882023-03-07 https://scifaro.com/en/abs/reverse-engineering-word-level-models-from-look-up-table-netlists-2303.027622023-03-07 https://scifaro.com/en/abs/in-storage-domain-specific-acceleration-for-serverless-computing-2303.034832024-03-26 https://scifaro.com/en/abs/sparta-spatial-acceleration-for-efficient-and-scalable-horizontal-diffusion-weather-stencil-computation-2303.035092023-05-10 https://scifaro.com/en/abs/boosting-the-3d-thermal-aware-floorplanning-problem-through-a-master-worker-parallel-moea-2303.037792023-03-08 https://scifaro.com/en/abs/xel-fpgas-an-end-to-end-automated-exploration-framework-for-approximate-accelerators-in-fpga-based-systems-2303.047342023-08-09 https://scifaro.com/en/abs/hardware-acceleration-of-neural-graphics-2303.057352023-04-14 https://scifaro.com/en/abs/word-level-structure-identification-in-fpga-designs-using-cell-proximity-information-2303.074052023-03-15 https://scifaro.com/en/abs/infra-red-in-situ-iris-inspection-of-silicon-2303.074062023-03-15 https://scifaro.com/en/abs/study-on-the-data-storage-technology-of-mini-airborne-radar-based-on-machine-learning-2303.074072023-03-15 https://scifaro.com/en/abs/improving-dram-performance-reliability-and-security-by-rigorously-understanding-intrinsic-dram-operation-2303.074452023-03-15 https://scifaro.com/en/abs/statistical-hardware-design-with-multi-model-active-learning-2303.080542023-04-11 https://scifaro.com/en/abs/gamora-graph-learning-based-symbolic-reasoning-for-large-scale-boolean-networks-2303.082562023-06-13 https://scifaro.com/en/abs/a-high-performance-accelerator-for-super-resolution-processing-on-embedded-gpu-2303.089992023-04-04 https://scifaro.com/en/abs/multi-electrostatic-fpga-placement-considering-slicel-slicem-heterogeneity-clock-feasibility-and-timing-optimization-2303.093052023-03-17 https://scifaro.com/en/abs/vpu-em-an-event-based-modeling-framework-to-evaluate-npu-performance-and-power-efficiency-at-scale-2303.102712023-03-21 https://scifaro.com/en/abs/unraveling-the-integration-of-deep-machine-learning-in-fpga-cad-flow-a-concise-survey-and-future-insights-2303.105082023-03-21 https://scifaro.com/en/abs/efficient-deadlock-avoidance-for-2d-mesh-nocs-that-use-oq-or-voq-routers-2303.105262024-02-20 https://scifaro.com/en/abs/simulation-environment-with-customized-risc-v-instructions-for-logic-in-memory-architectures-2303.121282023-03-28 https://scifaro.com/en/abs/a-cycle-accurate-soft-error-vulnerability-analysis-framework-for-fpga-based-designs-2303.122692023-03-23 https://scifaro.com/en/abs/system-and-design-technology-co-optimization-of-sot-mram-for-high-performance-ai-accelerator-memory-system-2303.123102023-11-15 https://scifaro.com/en/abs/a-cycle-level-unified-dram-cache-controller-model-for-3dxpoint-memory-systems-in-gem5-2303.130262023-03-24 https://scifaro.com/en/abs/enabling-design-space-exploration-of-dram-caches-in-emerging-memory-systems-2303.130292023-03-24 https://scifaro.com/en/abs/learnedftl-a-learning-based-page-level-ftl-for-reducing-double-reads-in-flash-based-ssds-2303.132262024-04-26 https://scifaro.com/en/abs/computing-and-compressing-electron-repulsion-integrals-on-fpgas-2303.136322023-03-27 https://scifaro.com/en/abs/on-the-susceptibility-of-qdi-circuits-to-transient-faults-2303.141062023-07-07 https://scifaro.com/en/abs/ima-gnn-in-memory-acceleration-of-centralized-and-decentralized-graph-neural-networks-at-the-edge-2303.141622023-03-27 https://scifaro.com/en/abs/maple-a-processing-element-for-row-wise-product-based-sparse-tensor-accelerators-2303.151992023-03-28 https://scifaro.com/en/abs/machine-learning-for-microprocessor-performance-bug-localization-2303.152802023-03-28 https://scifaro.com/en/abs/the-mirage-of-breaking-mirage-refuting-the-hpca-2023-paper-are-randomized-caches-truly-random-2303.156732023-03-29 https://scifaro.com/en/abs/evolutionary-design-of-the-memory-subsystem-2303.160742023-03-29 https://scifaro.com/en/abs/gnnbuilder-an-automated-framework-for-generic-graph-neural-network-accelerator-generation-simulation-and-optimization-2303.164592025-10-27 https://scifaro.com/en/abs/rpu-the-ring-processing-unit-2303.171182023-04-14 https://scifaro.com/en/abs/harflow3d-a-latency-oriented-3d-cnn-accelerator-toolflow-for-har-on-fpga-devices-2303.172182024-03-05 https://scifaro.com/en/abs/mempool-a-scalable-manycore-architecture-with-a-low-latency-shared-l1-memory-2303.177422023-11-29 https://scifaro.com/en/abs/darkside-a-heterogeneous-risc-v-compute-cluster-for-extreme-edge-on-chip-dnn-inference-and-training-2303.179542023-04-03 https://scifaro.com/en/abs/proceedings-of-the-3rd-workshop-on-open-source-design-automation-osda-2023-2303.180242023-04-03 https://scifaro.com/en/abs/is-this-computing-accelerator-evaluation-full-of-hot-air-2304.010122023-04-04 https://scifaro.com/en/abs/tpu-v4-an-optically-reconfigurable-supercomputer-for-machine-learning-with-hardware-support-for-embeddings-2304.014332023-04-24 https://scifaro.com/en/abs/reduced-precision-floating-point-arithmetic-in-systolic-arrays-with-skewed-pipelines-2304.016682023-09-11 https://scifaro.com/en/abs/fourierpim-high-throughput-in-memory-fast-fourier-transform-and-polynomial-multiplication-2304.023362023-04-06 https://scifaro.com/en/abs/hog-2023-1-a-collaborative-management-tool-to-handle-git-based-hdl-repository-2304.024372023-04-13 https://scifaro.com/en/abs/spade-an-expression-based-hdl-with-pipelines-2304.030792023-04-07 https://scifaro.com/en/abs/locate-low-power-viterbi-decoder-exploration-using-approximate-adders-2304.032572023-04-07 https://scifaro.com/en/abs/camj-enabling-system-level-energy-modeling-and-architectural-exploration-for-in-sensor-visual-computing-2304.033202023-04-10 https://scifaro.com/en/abs/imagen-a-general-framework-for-generating-memory-and-power-efficient-image-processing-accelerators-2304.033522023-04-10 https://scifaro.com/en/abs/bramac-compute-in-bram-architectures-for-multiply-accumulate-on-fpgas-2304.039742023-04-11 https://scifaro.com/en/abs/respect-reinforcement-learning-based-edge-scheduling-on-pipelined-coral-edge-tpus-2304.047162023-04-11 https://scifaro.com/en/abs/custom-memory-design-for-logic-in-memory-drawbacks-and-improvements-over-conventional-memories-2304.049952023-04-14 https://scifaro.com/en/abs/enhancement-in-reliability-for-multi-core-system-consisting-of-one-instruction-cores-2304.050722023-04-12 https://scifaro.com/en/abs/high-performance-and-scalable-software-based-nvme-virtualization-mechanism-with-i-o-queues-passthrough-2304.051482023-04-12 https://scifaro.com/en/abs/towards-power-characterization-of-fpga-architectures-to-enable-open-source-power-estimation-using-micro-benchmarks-2304.053262023-04-12 https://scifaro.com/en/abs/performance-study-of-partitioned-caches-in-asymmetric-multi-core-processors-2304.054422023-04-13 https://scifaro.com/en/abs/programming-language-assisted-waveform-analysis-a-case-study-on-the-instruction-performance-of-serv-2304.058372023-04-13 https://scifaro.com/en/abs/algorithms-and-hardware-for-efficient-processing-of-logic-based-neural-networks-2304.062992023-04-14 https://scifaro.com/en/abs/an-automotive-case-study-on-the-limits-of-approximation-for-object-detection-2304.063272023-04-14 https://scifaro.com/en/abs/dgnn-booster-a-generic-fpga-accelerator-framework-for-dynamic-graph-neural-network-inference-2304.068312023-04-17 https://scifaro.com/en/abs/spchar-characterizing-the-sparse-puzzle-via-decision-trees-2304.069442024-07-31 https://scifaro.com/en/abs/lightrw-fpga-accelerated-graph-dynamic-random-walks-2304.070042023-04-24 https://scifaro.com/en/abs/a-reconfigurable-linear-rf-analog-processor-for-realizing-microwave-artificial-neural-network-2304.073782023-08-04 https://scifaro.com/en/abs/implementation-of-digital-circuits-on-three-dimensional-fpgas-using-simulated-annealing-2304.074762023-04-18 https://scifaro.com/en/abs/olive-accelerating-large-language-models-via-hardware-friendly-outlier-victim-pair-quantization-2304.074932023-04-18 https://scifaro.com/en/abs/high-speed-and-energy-efficient-non-binary-computing-with-polymorphic-electro-optic-circuits-and-architectures-2304.076082023-04-18 https://scifaro.com/en/abs/teaal-a-declarative-framework-for-modeling-sparse-tensor-accelerators-2304.079312024-06-13 https://scifaro.com/en/abs/raella-reforming-the-arithmetic-for-efficient-low-resolution-and-low-loss-analog-pim-no-retraining-required-2304.079352023-04-18 https://scifaro.com/en/abs/dynamically-reconfigurable-variable-precision-sparse-dense-matrix-acceleration-in-tensorflow-lite-2304.082112023-04-18 https://scifaro.com/en/abs/atheena-a-toolflow-for-hardware-early-exit-network-automation-2304.084002025-04-15 https://scifaro.com/en/abs/nps-a-framework-for-accurate-program-sampling-using-graph-neural-network-2304.088802023-04-19 https://scifaro.com/en/abs/heterogeneous-integration-of-in-memory-analog-computing-architectures-with-tensor-processing-units-2304.092582023-04-20 https://scifaro.com/en/abs/egalitarian-oram-wear-leveling-for-oram-2304.094112023-04-20 https://scifaro.com/en/abs/baugh-wooley-multiplication-for-the-riscv-processor-2304.099522023-04-21 https://scifaro.com/en/abs/uleen-a-novel-architecture-for-ultra-low-energy-edge-neural-networks-2304.106182023-04-24 https://scifaro.com/en/abs/modular-hardware-design-with-timeline-types-2304.106462023-04-24 https://scifaro.com/en/abs/integrating-per-stream-stat-tracking-into-accel-sim-2304.111362023-09-06 https://scifaro.com/en/abs/a-deep-neural-network-deployment-based-on-resistive-memory-accelerator-simulation-2304.113372024-09-02 https://scifaro.com/en/abs/optimized-real-time-assembly-in-a-risc-simulator-2304.123092023-04-25 https://scifaro.com/en/abs/instant-3d-instant-neural-radiance-field-training-towards-on-device-ar-vr-3d-reconstruction-2304.124672025-03-31 https://scifaro.com/en/abs/design-optimization-for-high-performance-computing-using-fpga-2304.124742023-04-26 https://scifaro.com/en/abs/evaluating-the-energy-measurements-of-the-ibm-power9-on-chip-controller-2304.126462023-04-26 https://scifaro.com/en/abs/low-power-data-streaming-in-systolic-arrays-with-bus-invert-coding-and-zero-value-clock-gating-2304.126912023-09-11 https://scifaro.com/en/abs/dynamic-ineffectuality-based-clustered-architectures-2304.127622023-04-26 https://scifaro.com/en/abs/salsa-simulated-annealing-based-loop-ordering-scheduler-for-dnn-accelerators-2304.129312024-06-17 https://scifaro.com/en/abs/low-latency-online-multiplier-with-reduced-activities-and-minimized-interconnect-for-inner-product-arrays-2304.129462023-05-17 https://scifaro.com/en/abs/efat-improving-the-effectiveness-of-fault-aware-training-for-mitigating-permanent-faults-in-dnn-hardware-accelerators-2304.129492023-04-26 https://scifaro.com/en/abs/probe3-0-a-systematic-framework-for-design-technology-pathfinding-with-improved-design-enablement-2304.132152023-04-27 https://scifaro.com/en/abs/multi-criteria-hardware-trojan-detection-a-reinforcement-learning-approach-2304.132322023-04-27 https://scifaro.com/en/abs/scv-gnn-sparse-compressed-vector-based-graph-neural-network-aggregation-2304.135322023-07-14 https://scifaro.com/en/abs/accelerating-genome-analysis-via-algorithm-architecture-co-design-2305.004922023-06-01 https://scifaro.com/en/abs/modeling-and-analysis-of-analog-non-volatile-devices-for-compute-in-memory-applications-2305.006182023-05-02 https://scifaro.com/en/abs/design-space-exploration-and-optimization-for-carbon-efficient-extended-reality-systems-2305.018312023-05-04 https://scifaro.com/en/abs/a-quantitative-analysis-and-guidelines-of-data-streaming-accelerator-in-modern-intel-xeon-scalable-processors-2305.024802024-01-31 https://scifaro.com/en/abs/neuropuls-neuromorphic-energy-efficient-secure-accelerators-based-on-phase-change-materials-augmented-silicon-photonics-2305.031392023-08-31 https://scifaro.com/en/abs/camel-co-designing-ai-models-and-embedded-drams-for-efficient-on-device-learning-2305.031482023-12-27 https://scifaro.com/en/abs/convpim-evaluating-digital-processing-in-memory-through-convolutional-neural-network-acceleration-2305.041222023-05-09 https://scifaro.com/en/abs/flex-sfu-accelerating-dnn-activation-functions-by-non-uniform-piecewise-approximation-2305.045462023-05-09 https://scifaro.com/en/abs/cheshire-a-lightweight-linux-capable-risc-v-host-platform-for-domain-specific-accelerator-plug-in-2305.047602023-07-07 https://scifaro.com/en/abs/a-case-for-cxl-centric-server-processors-2305.050332023-05-10 https://scifaro.com/en/abs/a-high-performance-energy-efficient-modular-dma-engine-architecture-2305.052402023-11-15 https://scifaro.com/en/abs/vedliot-next-generation-accelerated-aiot-systems-and-applications-2305.053882023-05-10 https://scifaro.com/en/abs/sparse-stream-semantic-registers-a-lightweight-isa-extension-accelerating-general-sparse-linear-algebra-2305.055592023-10-03 https://scifaro.com/en/abs/characterizing-the-impact-of-last-level-cache-replacement-policies-on-big-data-workloads-2305.066962025-10-24 https://scifaro.com/en/abs/a-machine-learning-approach-to-improving-timing-consistency-between-global-route-and-detailed-route-2305.069172023-10-04 https://scifaro.com/en/abs/big-percival-exploring-the-native-use-of-64-bit-posit-arithmetic-in-scientific-computing-2305.069462024-03-15 https://scifaro.com/en/abs/echoes-a-200-gops-w-frequency-domain-soc-with-fft-processor-and-i2s-dsp-for-flexible-data-acquisition-from-microphone-arrays-2305.073252023-05-15 https://scifaro.com/en/abs/daism-digital-approximate-in-sram-multiplier-based-accelerator-for-dnn-training-and-inference-2305.073762024-01-19 https://scifaro.com/en/abs/spade-sparse-pillar-based-3d-object-detection-accelerator-for-autonomous-driving-2305.075222024-01-17 https://scifaro.com/en/abs/venice-improving-solid-state-drive-parallelism-at-low-cost-via-conflict-free-accesses-2305.077682023-05-16 https://scifaro.com/en/abs/by-software-branch-prediction-in-loops-2305.083172023-06-13 https://scifaro.com/en/abs/marsellus-a-heterogeneous-risc-v-ai-iot-end-node-soc-with-2-to-8b-dnn-acceleration-and-30-boost-adaptive-body-biasing-2305.084152023-11-29 https://scifaro.com/en/abs/floonoc-a-multi-tbps-wide-noc-for-heterogeneous-axi4-traffic-2305.085622023-08-29 https://scifaro.com/en/abs/newad-a-register-map-automation-tool-for-verilog-2305.096572023-05-17 https://scifaro.com/en/abs/analognas-a-neural-network-design-framework-for-accurate-inference-with-analog-in-memory-computing-2305.104592023-05-19 https://scifaro.com/en/abs/understanding-interactions-between-chip-architecture-and-uncertainties-in-semiconductor-supply-and-demand-2305.110592023-05-19 https://scifaro.com/en/abs/faq-mitigating-the-impact-of-faults-in-the-weight-memory-of-dnn-accelerators-through-fault-aware-quantization-2305.125902023-05-23 https://scifaro.com/en/abs/reduce-a-framework-for-reducing-the-overheads-of-fault-aware-retraining-2305.125952023-05-23 https://scifaro.com/en/abs/highlight-efficient-and-flexible-dnn-acceleration-with-hierarchical-structured-sparsity-2305.127182023-10-03 https://scifaro.com/en/abs/imbue-in-memory-boolean-to-current-inference-architecture-for-tsetlin-machines-2305.129142023-05-23 https://scifaro.com/en/abs/accelerating-fpga-based-wi-fi-transceiver-design-and-prototyping-by-high-level-synthesis-2305.133512023-05-24 https://scifaro.com/en/abs/transceiver-design-and-performance-analysis-for-lr-fhss-based-direct-to-satellite-iot-2305.137792023-05-29 https://scifaro.com/en/abs/bulk-switching-memristor-based-compute-in-memory-module-for-deep-neural-network-training-2305.145472024-02-16 https://scifaro.com/en/abs/gradient-descent-based-programming-of-analog-in-memory-computing-cores-2305.166472023-05-29 https://scifaro.com/en/abs/graphtensor-comprehensive-gnn-acceleration-framework-for-efficient-parallel-processing-of-massive-datasets-2305.174692023-05-30 https://scifaro.com/en/abs/an-evaluation-of-a-microprocessor-with-two-independent-hardware-execution-threads-coupled-through-a-shared-cache-2305.177732023-05-30 https://scifaro.com/en/abs/open-source-gemm-hardware-kernels-generator-toward-numerically-tailored-computations-2305.183282023-05-31 https://scifaro.com/en/abs/pqa-exploring-the-potential-of-product-quantization-in-dnn-hardware-acceleration-2305.183342024-04-01 https://scifaro.com/en/abs/benchmarking-and-modeling-of-analog-and-digital-sram-in-memory-computing-architectures-2305.183352023-05-31 https://scifaro.com/en/abs/hardware-aware-training-techniques-for-improving-robustness-of-ex-situ-neural-network-transfer-onto-passive-tio2-reram-crossbars-2305.184952023-05-31 https://scifaro.com/en/abs/edge-moe-memory-efficient-multi-task-vision-transformer-architecture-with-task-level-sparsity-via-mixture-of-experts-2305.186912023-09-14 https://scifaro.com/en/abs/automm-energy-efficient-multi-data-type-matrix-multiply-design-on-heterogeneous-programmable-system-on-chip-2305.186982023-05-31 https://scifaro.com/en/abs/nicepim-design-space-exploration-for-processing-in-memory-dnn-accelerators-with-3d-stacked-dram-2305.190412023-12-22 https://scifaro.com/en/abs/fpgahart-a-toolflow-for-throughput-oriented-acceleration-of-3d-cnns-for-har-onto-fpgas-2305.198962024-03-05 https://scifaro.com/en/abs/redsea-automated-acceleration-of-triangular-solver-on-supercloud-heterogeneous-systems-2305.199172023-06-01 https://scifaro.com/en/abs/memory-centric-computing-2305.200002023-09-15 https://scifaro.com/en/abs/a-novel-fault-tolerant-logic-style-with-self-checking-capability-2306.008442023-06-02 https://scifaro.com/en/abs/fifty-years-of-isca-a-data-driven-retrospective-on-key-trends-2306.039642023-11-21 https://scifaro.com/en/abs/s-3-increasing-gpu-utilization-during-generative-inference-for-higher-throughput-2306.060002023-06-12 https://scifaro.com/en/abs/netgap-a-graph-grammar-approach-for-concept-design-of-networked-platforms-with-extra-functional-requirements-2306.077782024-02-09 https://scifaro.com/en/abs/safebet-secure-simple-and-fast-speculative-execution-2306.077852023-06-14 https://scifaro.com/en/abs/archgym-an-open-source-gymnasium-for-machine-learning-assisted-architecture-design-2306.088882023-06-16 https://scifaro.com/en/abs/ultra8t-a-sub-threshold-8t-sram-with-leakage-detection-2306.089362024-04-09 https://scifaro.com/en/abs/an-energy-efficient-generic-accuracy-configurable-multiplier-based-on-block-level-voltage-overscaling-2306.090322023-07-06 https://scifaro.com/en/abs/x-rel-energy-efficient-and-low-overhead-approximate-reliability-framework-for-error-tolerant-applications-deployed-in-critical-systems-2306.090372023-07-06 https://scifaro.com/en/abs/eco-chip-estimation-of-carbon-footprint-of-chiplet-based-architectures-for-sustainable-vlsi-2306.094342024-02-15 https://scifaro.com/en/abs/leveraging-residue-number-system-for-designing-high-precision-analog-deep-neural-network-accelerators-2306.094812023-06-19 https://scifaro.com/en/abs/controlpulp-a-risc-v-on-chip-parallel-power-controller-for-many-core-hpc-processors-with-fpga-based-hardware-in-the-loop-power-and-thermal-emulation-2306.095012024-02-22 https://scifaro.com/en/abs/retrospective-eie-efficient-inference-engine-on-sparse-and-compressed-neural-network-2306.095522023-06-19 https://scifaro.com/en/abs/sparq-a-custom-risc-v-vector-processor-for-efficient-sub-byte-quantized-inference-2306.099052023-06-19 https://scifaro.com/en/abs/pimminer-a-high-performance-pim-architecture-aware-graph-mining-framework-2306.102572023-06-21 https://scifaro.com/en/abs/a-multithread-aes-accelerator-for-cyber-physical-systems-2306.107882023-06-21 https://scifaro.com/en/abs/understanding-the-effects-of-permanent-faults-in-gpu-s-parallelism-management-and-control-units-2306.108562023-10-03 https://scifaro.com/en/abs/an-introduction-to-the-compute-express-link-cxl-interconnect-2306.112272024-05-09 https://scifaro.com/en/abs/lightridge-an-end-to-end-agile-design-framework-for-diffractive-optical-neural-networks-2306.112682023-10-05 https://scifaro.com/en/abs/low-latency-edge-classification-gnn-for-particle-trajectory-tracking-on-fpgas-2306.113302023-06-28 https://scifaro.com/en/abs/a-versatility-performance-balanced-hardware-architecture-for-scene-text-detection-2306.113512023-06-21 https://scifaro.com/en/abs/design-of-energy-harvesting-based-hardware-for-iot-applications-2306.120192023-06-22 https://scifaro.com/en/abs/python-framework-for-modular-and-parametric-spice-netlists-generation-2306.122242023-06-22 https://scifaro.com/en/abs/to-spike-or-not-to-spike-a-quantitative-comparison-of-snn-and-cnn-fpga-implementations-2306.127422023-06-23 https://scifaro.com/en/abs/analysing-mechanisms-for-virtual-channel-management-in-low-diameter-networks-2306.130422024-02-02 https://scifaro.com/en/abs/fpga-implementation-of-convolutional-neural-network-for-real-time-handwriting-recognition-2306.135572023-06-27 https://scifaro.com/en/abs/heterogeneous-alu-architecture-power-aware-system-2306.150922023-06-28 https://scifaro.com/en/abs/c3s-micro-architectural-enhancement-spike-encoder-block-and-relaxing-gamma-clock-asynchronous-2306.150932023-06-28 https://scifaro.com/en/abs/a-survey-on-deep-learning-hardware-accelerators-for-heterogeneous-hpc-platforms-2306.155522025-04-11 https://scifaro.com/en/abs/retrospective-a-scalable-processing-in-memory-accelerator-for-parallel-graph-processing-2306.155772023-06-28 https://scifaro.com/en/abs/kapla-pragmatic-representation-and-fast-solving-of-scalable-nn-accelerator-dataflow-2306.156762023-06-29 https://scifaro.com/en/abs/retrospective-corona-system-implications-of-emerging-nanophotonic-technology-2306.156882023-06-29 https://scifaro.com/en/abs/retrospective-raidr-retention-aware-intelligent-dram-refresh-2306.160242023-06-29 https://scifaro.com/en/abs/retrospective-an-experimental-study-of-data-retention-behavior-in-modern-dram-devices-implications-for-retention-time-profiling-mechanisms-2306.160372023-06-29 https://scifaro.com/en/abs/exploration-and-analysis-of-combinations-of-hamming-codes-in-32-bit-memories-2306.162592023-07-14 https://scifaro.com/en/abs/redy-a-novel-reram-centric-dynamic-quantization-approach-for-energy-efficient-cnn-inference-2306.162982023-06-29 https://scifaro.com/en/abs/openparf-an-open-source-placement-and-routing-framework-for-large-scale-heterogeneous-fpgas-with-deep-learning-toolkit-2306.166652023-06-30 https://scifaro.com/en/abs/performance-analysis-of-dnn-inference-training-with-convolution-and-non-convolution-operations-2306.167672025-01-28 https://scifaro.com/en/abs/hashmem-pim-based-hashmap-accelerator-2306.177212023-07-03 https://scifaro.com/en/abs/a-3-tops-w-risc-v-parallel-cluster-for-inference-of-fine-grain-mixed-precision-quantized-neural-networks-2307.010562023-07-04 https://scifaro.com/en/abs/pimcomp-a-universal-compilation-framework-for-crossbar-based-pim-dnn-accelerators-2307.014752023-07-06 https://scifaro.com/en/abs/ghost-a-graph-neural-network-accelerator-using-silicon-photonics-2307.017822023-07-06 https://scifaro.com/en/abs/chiplet-cloud-building-ai-supercomputers-for-serving-large-generative-language-models-2307.026662024-05-22 https://scifaro.com/en/abs/tl-nvsram-cim-ultra-high-density-three-level-reram-assisted-computing-in-nvsram-with-dc-power-free-restore-and-ternary-mac-operations-2307.027172024-01-12 https://scifaro.com/en/abs/towards-efficient-control-flow-handling-in-spatial-architecture-via-architecting-the-control-flow-plane-2307.028472023-09-20 https://scifaro.com/en/abs/ita-an-energy-efficient-attention-and-softmax-accelerator-for-quantized-transformers-2307.034932024-07-29 https://scifaro.com/en/abs/neuroblend-towards-low-power-yet-accurate-neural-network-based-inference-engine-blending-binary-and-fixed-point-convolutions-2307.037842024-05-02 https://scifaro.com/en/abs/memory-immersed-collaborative-digitization-for-area-efficient-compute-in-memory-deep-learning-2307.038632023-07-11 https://scifaro.com/en/abs/a-survey-of-spiking-neural-network-accelerator-on-fpga-2307.039102023-07-11 https://scifaro.com/en/abs/towards-efficient-in-memory-computing-hardware-for-quantized-neural-networks-state-of-the-art-open-challenges-and-perspectives-2307.039362023-08-02 https://scifaro.com/en/abs/towards-a-risc-v-open-platform-for-next-generation-automotive-ecus-2307.041482023-07-11 https://scifaro.com/en/abs/a-137-5-tops-w-sram-compute-in-memory-macro-with-9-b-memory-cell-embedded-adcs-and-signal-margin-enhancement-techniques-for-ai-edge-applications-2307.059442023-07-20 https://scifaro.com/en/abs/corona-system-implications-of-emerging-nanophotonic-technology-2307.062942023-07-13 https://scifaro.com/en/abs/ageing-analysis-of-embedded-sram-on-a-large-scale-testbed-using-machine-learning-2307.066932023-07-14 https://scifaro.com/en/abs/prefender-a-prefetching-defender-against-cache-side-channel-attacks-as-a-pretender-2307.067562024-05-16 https://scifaro.com/en/abs/pass-exploiting-post-activation-sparsity-in-streaming-architectures-for-cnn-acceleration-2307.078212023-07-18 https://scifaro.com/en/abs/exploiting-fpga-capabilities-for-accelerated-biomedical-computing-2307.079142023-07-18 https://scifaro.com/en/abs/3d-carbon-an-analytical-carbon-modeling-tool-for-3d-and-2-5d-integrated-circuits-2307.080602024-06-14 https://scifaro.com/en/abs/egpu-a-750-mhz-class-soft-gpgpu-for-fpga-2307.083782023-07-18 https://scifaro.com/en/abs/lightweight-ml-based-runtime-prefetcher-selection-on-many-core-platforms-2307.086352023-07-18 https://scifaro.com/en/abs/impact-of-gate-level-clustering-on-automated-system-partitioning-of-3d-ics-2307.093082023-08-31 https://scifaro.com/en/abs/exploration-of-time-reversal-for-wireless-communications-within-computing-packages-2307.108202023-08-14 https://scifaro.com/en/abs/probabilistic-compute-in-memory-design-for-efficient-markov-chain-monte-carlo-sampling-2307.108662023-12-12 https://scifaro.com/en/abs/modular-dfr-digital-delayed-feedback-reservoir-model-for-enhancing-design-flexibility-2307.110942023-07-24 https://scifaro.com/en/abs/approximate-computing-survey-part-i-terminology-and-software-hardware-approximation-techniques-2307.111242025-03-21 https://scifaro.com/en/abs/approximate-computing-survey-part-ii-application-specific-architectural-approximation-techniques-and-applications-2307.111282025-03-21 https://scifaro.com/en/abs/envisioning-a-safety-island-to-enable-hpc-devices-in-safety-critical-domains-2307.119402023-07-25 https://scifaro.com/en/abs/varsim-a-fast-process-variation-aware-thermal-modeling-methodology-using-green-s-functions-2307.121192023-07-25 https://scifaro.com/en/abs/neuromorphic-neuromodulation-towards-the-next-generation-of-on-device-ai-revolution-in-electroceuticals-2307.124712023-07-31 https://scifaro.com/en/abs/hihgnn-accelerating-hgnns-through-parallelism-and-data-reusability-exploitation-2307.127652024-04-29 https://scifaro.com/en/abs/safels-toward-building-a-lockstep-noel-v-core-2307.154362023-07-31 https://scifaro.com/en/abs/a-dataflow-compiler-for-efficient-llm-inference-using-custom-microscaling-formats-2307.155172024-04-22 https://scifaro.com/en/abs/implementation-of-fast-and-power-efficient-sec-daec-and-sec-daec-taec-codecs-on-fpga-2307.161952023-08-01 https://scifaro.com/en/abs/patronoc-parallel-axi-transport-reducing-overhead-for-networks-on-chip-targeting-multi-accelerator-dnn-platforms-at-the-edge-2308.001542023-08-02 https://scifaro.com/en/abs/an-empirical-evaluation-of-aridem-using-matrix-multiplication-2308.006612023-08-02 https://scifaro.com/en/abs/pathfinding-future-pim-architectures-by-demystifying-a-commercial-pim-technology-2308.008462024-03-08 https://scifaro.com/en/abs/floorplet-performance-aware-floorplan-framework-for-chiplet-integration-2308.016722023-12-12 https://scifaro.com/en/abs/the-data-conversion-bottleneck-in-analog-computing-accelerators-2308.017192024-01-02 https://scifaro.com/en/abs/ieda-an-open-source-intelligent-physical-implementation-toolkit-and-library-2308.018572023-08-04 https://scifaro.com/en/abs/evaluation-of-stt-mram-as-a-scratchpad-for-training-in-ml-accelerators-2308.020242023-08-07 https://scifaro.com/en/abs/work-in-progress-a-universal-instrumentation-platform-for-non-volatile-memories-2308.024002023-08-07 https://scifaro.com/en/abs/exploiting-on-chip-heterogeneity-of-versal-architecture-for-gnn-inference-acceleration-2308.027492023-08-08 https://scifaro.com/en/abs/fglqr-factor-graph-accelerator-of-lqr-control-for-autonomous-machines-2308.027682023-08-08 https://scifaro.com/en/abs/rv-cure-a-risc-v-capability-architecture-for-full-memory-safety-2308.029452023-08-08 https://scifaro.com/en/abs/leaps-topological-layout-adaptable-multi-die-fpga-placement-for-super-long-line-minimization-2308.032332024-02-05 https://scifaro.com/en/abs/ppu-design-and-implementation-of-a-pipelined-full-posit-processing-unit-2308.034252024-04-09 https://scifaro.com/en/abs/fpga-processor-in-memory-architectures-pims-overlay-or-overhaul-2308.039142023-12-11 https://scifaro.com/en/abs/collaborative-acceleration-for-fft-on-commercial-processing-in-memory-architectures-2308.039732023-08-09 https://scifaro.com/en/abs/core-interface-optimization-for-multi-core-neuromorphic-processors-2308.041712023-08-09 https://scifaro.com/en/abs/yak-an-asynchronous-bundled-data-pipeline-description-language-2308.041892023-08-09 https://scifaro.com/en/abs/cifher-a-chiplet-based-fhe-accelerator-with-a-resizable-structure-2308.048902024-04-02 https://scifaro.com/en/abs/fpga-resource-aware-structured-pruning-for-real-time-neural-networks-2308.051702025-04-21 https://scifaro.com/en/abs/machine-learning-aided-computer-architecture-design-for-cnn-inferencing-systems-2308.053642023-08-11 https://scifaro.com/en/abs/checkpoint-placement-for-systematic-fault-injection-campaigns-2308.055212023-08-11 https://scifaro.com/en/abs/inr-arch-a-dataflow-architecture-and-compiler-for-arbitrary-order-gradient-computations-in-implicit-neural-representation-processing-2308.059302025-10-27 https://scifaro.com/en/abs/accelerating-generic-graph-neural-networks-via-architecture-compiler-partition-method-co-design-2308.081742023-08-17 https://scifaro.com/en/abs/spocta-a-3d-sparse-convolution-accelerator-with-octree-encoding-based-map-search-and-inherent-sparsity-aware-processing-2308.092492023-08-21 https://scifaro.com/en/abs/parti-gem5-gem5-s-timing-mode-parallelised-2308.094452024-05-14 https://scifaro.com/en/abs/chateda-a-large-language-model-powered-autonomous-agent-for-eda-2308.102042024-09-24 https://scifaro.com/en/abs/ramulator-2-0-a-modern-modular-and-extensible-dram-simulator-2308.110302023-11-30 https://scifaro.com/en/abs/gsa-to-hdl-towards-principled-generation-of-dynamically-scheduled-circuits-2308.110482023-08-23 https://scifaro.com/en/abs/octopus-a-heterogeneous-in-network-computing-accelerator-enabling-deep-learning-for-network-2308.113122023-08-23 https://scifaro.com/en/abs/deepburning-mixq-an-open-source-mixed-precision-neural-network-accelerator-design-framework-for-fpgas-2308.113342023-08-23 https://scifaro.com/en/abs/safeti-traffic-injector-enhancement-for-effective-interference-testing-in-critical-real-time-systems-2308.115282023-08-23 https://scifaro.com/en/abs/accel-gcn-high-performance-gpu-accelerator-design-for-graph-convolution-networks-2308.118252023-08-24 https://scifaro.com/en/abs/dica-a-hardware-software-co-design-for-differential-checkpointing-in-intermittently-powered-devices-2308.128192023-08-28 https://scifaro.com/en/abs/implementing-performance-portability-of-high-performance-computing-programs-in-the-new-golden-age-of-chip-architecture-2308.138022023-08-29 https://scifaro.com/en/abs/an-efficient-fpga-based-accelerator-for-swin-transformer-2308.139222023-08-29 https://scifaro.com/en/abs/pypim-integrating-digital-processing-in-memory-from-microarchitectural-design-to-python-tensors-2308.140072024-10-01 https://scifaro.com/en/abs/key-technologies-and-application-for-radar-and-smart-video-fusion-in-perimeter-intrusion-alarm-system-2308.142522023-08-29 https://scifaro.com/en/abs/osa-hcim-on-the-fly-saliency-aware-hybrid-sram-cim-with-dynamic-precision-configuration-2308.150402023-11-22 https://scifaro.com/en/abs/pals-distributed-gradient-clocking-on-chip-2308.150982023-08-30 https://scifaro.com/en/abs/best-memory-architecture-exploration-under-parameters-variations-accelerated-with-machine-learning-2308.151122023-08-30 https://scifaro.com/en/abs/read-reliability-enhanced-accelerator-dataflow-optimization-using-critical-input-pattern-reduction-2308.156982023-08-31 https://scifaro.com/en/abs/on-chip-sensors-data-collection-and-analysis-for-soc-health-management-2308.159172023-08-31 https://scifaro.com/en/abs/hisep-q-a-highly-scalable-and-efficient-quantum-control-processor-for-superconducting-qubits-2308.167762024-01-03 https://scifaro.com/en/abs/security-verification-of-low-trust-architectures-2309.001812023-09-04 https://scifaro.com/en/abs/the-case-for-replication-aware-memory-error-protection-in-disaggregated-memory-2309.003042024-06-10 https://scifaro.com/en/abs/accelerating-lstm-based-high-rate-dynamic-system-models-2309.008012023-09-06 https://scifaro.com/en/abs/windmill-a-parameterized-and-pluggable-cgra-implemented-by-diag-design-flow-2309.012732023-09-06 https://scifaro.com/en/abs/scalable-hierarchical-instruction-cache-for-ultra-low-power-processors-clusters-2309.012992023-09-06 https://scifaro.com/en/abs/collective-communication-patterns-using-time-reversal-terahertz-links-at-the-chip-scale-2309.014282023-09-07 https://scifaro.com/en/abs/satay-a-streaming-architecture-toolflow-for-accelerating-yolo-models-on-fpga-devices-2309.015872023-09-06 https://scifaro.com/en/abs/adc-dac-free-analog-acceleration-of-deep-neural-networks-with-frequency-transformation-2309.017712023-09-06 https://scifaro.com/en/abs/hw-sw-codesign-for-robust-and-efficient-binarized-snns-by-capacitor-minimization-2309.021112023-09-06 https://scifaro.com/en/abs/vector-processing-for-mobile-devices-benchmark-and-analysis-2309.026802023-09-07 https://scifaro.com/en/abs/the-case-for-asymmetric-systolic-array-floorplanning-2309.029692023-09-14 https://scifaro.com/en/abs/automatic-multi-dimensional-pipelining-for-high-level-synthesis-of-dataflow-accelerators-2309.032032023-09-08 https://scifaro.com/en/abs/a-9-transistor-sram-featuring-array-level-xor-parallelism-with-secure-data-toggling-operation-2309.032042023-09-08 https://scifaro.com/en/abs/a-circuit-domain-generalization-framework-for-efficient-logic-synthesis-in-chip-design-2309.032082023-09-08 https://scifaro.com/en/abs/test-primitive-a-straightforward-method-to-decouple-march-2309.032142023-09-08 https://scifaro.com/en/abs/spaic-a-sub-mu-w-channel-16-channel-general-purpose-event-based-analog-front-end-with-dual-mode-encoders-2309.032212023-09-08 https://scifaro.com/en/abs/high-speed-7-2-compressor-using-a-fast-carry-generation-logic-based-on-sorting-network-2309.036432023-09-08 https://scifaro.com/en/abs/mapping-of-cnns-on-multi-core-rram-based-cim-architectures-2309.038052023-10-27 https://scifaro.com/en/abs/cxlmemuring-a-hardware-software-co-design-paradigm-for-asynchronous-and-flexible-parallel-cxl-memory-pool-access-2309.040112023-09-11 https://scifaro.com/en/abs/pyhgl-a-python-based-hardware-generation-language-framework-2309.048592023-09-12 https://scifaro.com/en/abs/design-of-a-low-power-high-gain-bio-medical-operational-amplifier-in-65nm-technology-using-gm-id-methodology-2309.048632023-09-12 https://scifaro.com/en/abs/fusefps-accelerating-farthest-point-sampling-with-fusing-kd-tree-construction-for-point-clouds-2309.050172024-03-28 https://scifaro.com/en/abs/dslot-nn-digit-serial-left-to-right-neural-network-accelerator-2309.060192023-09-25 https://scifaro.com/en/abs/accelerating-edge-ai-with-morpher-an-integrated-design-compilation-and-simulation-framework-for-cgras-2309.061272023-09-13 https://scifaro.com/en/abs/extending-and-defending-attacks-on-reset-operations-in-quantum-computers-2309.062812023-09-13 https://scifaro.com/en/abs/c4cam-a-compiler-for-cam-based-in-memory-accelerators-2309.064182023-09-13 https://scifaro.com/en/abs/meticulous-an-fpga-based-main-memory-emulator-for-system-software-studies-2309.065652023-09-14 https://scifaro.com/en/abs/optimized-implementation-of-neuromorphic-hats-algorithm-on-fpga-2309.070772023-09-14 https://scifaro.com/en/abs/a-survey-of-graph-pre-processing-methods-from-algorithmic-to-hardware-perspectives-2309.075812023-09-15 https://scifaro.com/en/abs/inclusive-pim-hardware-software-co-design-for-broad-acceleration-on-commercial-pim-architectures-2309.079842024-01-18 https://scifaro.com/en/abs/a-precision-scalable-risc-v-dnn-processor-with-on-device-learning-capability-at-the-extreme-edge-2309.081862024-03-28 https://scifaro.com/en/abs/exploration-of-tpus-for-ai-applications-2309.089182023-11-15 https://scifaro.com/en/abs/a-low-latency-fft-ifft-cascade-architecture-2309.090352024-03-21 https://scifaro.com/en/abs/generalized-gain-and-impedance-expressions-for-single-transistor-amplifiers-2309.091902023-09-19 https://scifaro.com/en/abs/using-llms-to-facilitate-formal-verification-of-rtl-2309.094372024-10-28 https://scifaro.com/en/abs/spatz-clustering-compact-risc-v-based-vector-units-to-maximize-computing-efficiency-2309.101372025-01-10 https://scifaro.com/en/abs/fast-and-reconfigurable-sort-in-memory-system-enabled-by-memristors-2309.103502023-09-20 https://scifaro.com/en/abs/flip-data-centric-edge-cgra-accelerator-2309.106232023-09-20 https://scifaro.com/en/abs/a-back-end-of-line-compatible-ferroelectric-analog-non-volatile-memory-2309.120512023-09-22 https://scifaro.com/en/abs/a-beol-compatible-2-terminals-ferroelectric-analog-non-volatile-memory-2309.120612023-09-22 https://scifaro.com/en/abs/high-conductance-ohmic-like-hfzro-4-ferroelectric-memristor-2309.120702023-09-22 https://scifaro.com/en/abs/aim-accelerating-arbitrary-precision-integer-multiplication-on-heterogeneous-reconfigurable-computing-platform-versal-acap-2309.122752023-09-22 https://scifaro.com/en/abs/axocs-scaling-fpga-based-approximate-operators-using-configuration-supersampling-2309.128302024-04-22 https://scifaro.com/en/abs/platform-aware-fpga-system-architecture-generation-based-on-mlir-2309.129172023-09-25 https://scifaro.com/en/abs/onnx-to-hardware-design-flow-for-the-generation-of-adaptive-neural-network-accelerators-on-fpgas-2309.133212023-09-26 https://scifaro.com/en/abs/axomap-designing-fpga-based-approximate-arithmetic-operators-using-mathematical-programming-2309.134452024-02-21 https://scifaro.com/en/abs/scalable-data-concentrator-with-baseline-interconnection-network-for-triggerless-data-acquisition-systems-2309.136902024-02-14 https://scifaro.com/en/abs/on-the-non-associativity-of-analog-computations-2309.142922023-09-26 https://scifaro.com/en/abs/design-and-optimization-of-residual-neural-network-accelerators-for-low-power-fpgas-using-high-level-synthesis-2309.156312023-11-03 https://scifaro.com/en/abs/evaluating-the-efficiency-of-software-only-techniques-to-detect-seu-and-set-in-microprocessors-2309.168762023-10-02 https://scifaro.com/en/abs/gateseeder-near-memory-cpu-fpga-acceleration-of-short-and-long-read-mapping-2309.170632023-10-02 https://scifaro.com/en/abs/tailors-accelerating-sparse-tensor-algebra-by-overbooking-buffer-capacity-2310.001922024-06-27 https://scifaro.com/en/abs/parallel-in-memory-wireless-computing-2310.002882023-10-03 https://scifaro.com/en/abs/a-dsp-shared-is-a-dsp-earned-hls-task-level-multi-pumping-for-high-performance-low-resource-designs-2310.003302024-01-01 https://scifaro.com/en/abs/yflows-systematic-dataflow-exploration-and-code-generation-for-efficient-neural-network-inference-using-simd-architectures-on-cpus-2310.005742023-11-27 https://scifaro.com/en/abs/a-resource-efficient-fir-filter-design-based-on-an-rag-improved-algorithm-2310.009122023-11-27 https://scifaro.com/en/abs/subtractor-based-cnn-inference-accelerator-2310.010222023-10-03 https://scifaro.com/en/abs/jugglepac-a-pipelined-accumulation-circuit-2310.013362025-09-22 https://scifaro.com/en/abs/simplepim-a-software-framework-for-productive-and-efficient-processing-in-memory-2310.018932023-10-04 https://scifaro.com/en/abs/trikarenos-a-fault-tolerant-risc-v-based-microcontroller-for-cubesats-in-28nm-2310.020452024-01-12 https://scifaro.com/en/abs/co-optimizing-cache-partitioning-and-multi-core-task-scheduling-exploit-cache-sensitivity-or-not-2310.029592023-10-05 https://scifaro.com/en/abs/demist-detection-and-mitigation-of-stealthy-analog-hardware-trojans-2310.039942023-10-09 https://scifaro.com/en/abs/victima-drastically-increasing-address-translation-reach-by-leveraging-underutilized-cache-resources-2310.041582024-01-08 https://scifaro.com/en/abs/swordfish-a-framework-for-evaluating-deep-neural-network-based-basecalling-using-computation-in-memory-with-non-ideal-memristors-2310.043662023-11-28 https://scifaro.com/en/abs/see-mcam-scalable-multi-bit-fefet-content-addressable-memories-for-energy-efficient-associative-search-2310.049402023-10-10 https://scifaro.com/en/abs/medusa-scalable-biometric-sensing-in-the-wild-through-distributed-mimo-radars-2310.055072024-10-24 https://scifaro.com/en/abs/gem5pred-predictive-approaches-for-gem5-simulation-time-2310.062902023-10-11 https://scifaro.com/en/abs/analytical-die-to-die-3d-placement-with-bistratal-wirelength-model-and-gpu-acceleration-2310.074242023-10-13 https://scifaro.com/en/abs/dag-aware-synthesis-orchestration-2310.078462024-07-16 https://scifaro.com/en/abs/sorting-it-out-in-hardware-a-state-of-the-art-survey-2310.079032023-10-13 https://scifaro.com/en/abs/a-risc-v-mcu-with-adaptive-reverse-body-bias-and-ultra-low-power-retention-mode-in-22-nm-fd-soi-2310.090942024-02-01 https://scifaro.com/en/abs/pim-gpt-a-hybrid-process-in-memory-accelerator-for-autoregressive-transformers-2310.093852024-04-16 https://scifaro.com/en/abs/g10-enabling-an-efficient-unified-gpu-memory-and-storage-architecture-with-smart-tensor-migrations-2310.094432023-10-17 https://scifaro.com/en/abs/wafer-scale-computing-advancements-challenges-and-future-perspectives-2310.095682023-10-17 https://scifaro.com/en/abs/fpga-implementation-of-otfs-modulation-for-6g-communication-systems-2310.096712023-10-17 https://scifaro.com/en/abs/ntt-pim-row-centric-architecture-and-mapping-for-efficient-number-theoretic-transform-on-pim-2310.097152023-10-17 https://scifaro.com/en/abs/fast-and-low-cost-approximate-multiplier-for-fpgas-using-dynamic-reconfiguration-2310.100532023-10-17 https://scifaro.com/en/abs/dappa-a-data-parallel-programming-framework-for-processing-in-memory-architectures-2310.101682025-04-23 https://scifaro.com/en/abs/reuse-kernels-or-activations-a-flexible-dataflow-for-low-latency-spectral-cnn-acceleration-2310.109022023-10-18 https://scifaro.com/en/abs/block-wise-mixed-precision-quantization-enabling-high-efficiency-for-practical-reram-based-dnn-accelerators-2310.121822023-10-31 https://scifaro.com/en/abs/post-layout-simulation-driven-analog-circuit-sizing-2310.140492023-10-24 https://scifaro.com/en/abs/amg-automated-efficient-approximate-multiplier-generator-for-fpgas-via-bayesian-optimization-2310.154952023-10-31 https://scifaro.com/en/abs/an-in-memory-architecture-for-high-performance-long-read-pre-alignment-filtering-2310.156342023-10-25 https://scifaro.com/en/abs/rampart-rowhammer-mitigation-and-repair-for-server-memory-systems-2310.163542023-10-26 https://scifaro.com/en/abs/design-space-exploration-of-sparsity-aware-application-specific-spiking-neural-network-accelerators-2310.167452023-10-27 https://scifaro.com/en/abs/all-rounder-a-flexible-ai-accelerator-with-diverse-data-format-support-and-morphable-structure-for-multi-dnn-processing-2310.167572025-03-03 https://scifaro.com/en/abs/enhancing-energy-efficiency-by-solving-the-throughput-bottleneck-of-lstm-cells-for-embedded-fpgas-2310.168422023-11-28 https://scifaro.com/en/abs/experimental-demonstration-of-non-stateful-in-memory-logic-with-1t1r-oxram-valence-change-mechanism-memristors-2310.168432023-10-27 https://scifaro.com/en/abs/hardware-algorithm-co-design-enabling-processing-in-pixel-in-memory-p2m-for-neuromorphic-vision-sensors-2310.168442023-10-27 https://scifaro.com/en/abs/pac-sim-simulation-of-multi-threaded-workloads-using-intelligent-live-sampling-2310.170892023-10-27 https://scifaro.com/en/abs/a-lightweight-compiler-assisted-register-file-cache-for-gpgpu-2310.175012023-10-27 https://scifaro.com/en/abs/acwa-an-ai-driven-cyber-physical-testbed-for-intelligent-water-systems-2310.176542023-10-30 https://scifaro.com/en/abs/an-energy-efficient-near-data-processing-accelerator-for-dnns-that-optimizes-data-accesses-2310.181812023-10-30 https://scifaro.com/en/abs/hypersparse-traffic-matrix-construction-using-graphblas-on-a-dpu-2310.183342023-10-31 https://scifaro.com/en/abs/supporting-custom-instructions-with-the-llvm-compiler-for-risc-v-processor-2310.183532023-10-31 https://scifaro.com/en/abs/cmos-based-single-cycle-in-memory-xor-xnor-2310.183752023-10-31 https://scifaro.com/en/abs/ddc-pim-efficient-algorithm-architecture-co-design-for-doubling-data-capacity-of-sram-based-processing-in-memory-2310.204242023-11-01 https://scifaro.com/en/abs/fault-tolerant-design-approach-based-on-approximate-computing-2311.003282023-11-02 https://scifaro.com/en/abs/virtual-peripheral-in-the-loop-a-hardware-in-the-loop-strategy-to-bridge-the-vp-rtl-design-gap-2311.004422023-11-02 https://scifaro.com/en/abs/nsf-integrated-circuit-research-education-and-workforce-development-workshop-final-report-2311.020552023-11-06 https://scifaro.com/en/abs/m4bram-mixed-precision-matrix-matrix-multiplication-in-fpga-block-rams-2311.027582023-11-07 https://scifaro.com/en/abs/edge-ai-inference-in-heterogeneous-constrained-computing-feasibility-and-opportunities-2311.033752023-11-08 https://scifaro.com/en/abs/hida-a-hierarchical-dataflow-compiler-for-high-level-synthesis-2311.033792023-11-08 https://scifaro.com/en/abs/leveraging-high-level-synthesis-and-large-language-models-to-generate-simulate-and-deploy-a-uniform-random-number-generator-hardware-design-2311.034892024-11-26 https://scifaro.com/en/abs/accelerating-unstructured-spgemm-using-structured-in-situ-computing-2311.038262023-11-08 https://scifaro.com/en/abs/preliminary-design-of-scalable-hardware-integrated-platform-for-llrf-application-2311.038412023-11-08 https://scifaro.com/en/abs/how-charles-babbage-invented-the-computer-2311.043712023-11-09 https://scifaro.com/en/abs/evaluating-emerging-ai-ml-accelerators-ipu-rdu-and-nvidia-amd-gpus-2311.044172024-03-20 https://scifaro.com/en/abs/kid-a-hardware-design-framework-targeting-unified-ntt-multiplication-for-crystals-kyber-and-crystals-dilithium-on-fpga-2311.045812023-11-09 https://scifaro.com/en/abs/autows-automate-weights-streaming-in-layer-wise-pipelined-dnn-accelerators-2311.047642023-11-09 https://scifaro.com/en/abs/a-lightweight-architecture-for-real-time-neuronal-spike-classification-2311.048082024-04-02 https://scifaro.com/en/abs/maxeva-maximizing-the-efficiency-of-matrix-multiplication-on-versal-ai-engine-2311.049802023-11-15 https://scifaro.com/en/abs/just-in-time-quantization-with-processing-in-memory-for-efficient-ml-training-2311.050342023-11-10 https://scifaro.com/en/abs/ml-based-real-time-control-at-the-edge-an-approach-using-hls4ml-2311.057162023-11-13 https://scifaro.com/en/abs/rapidchiplet-a-toolchain-for-rapid-design-space-exploration-of-chiplet-architectures-2311.060812025-03-19 https://scifaro.com/en/abs/indexmac-a-custom-risc-v-vector-instruction-to-accelerate-structured-sparse-matrix-multiplications-2311.072412023-11-14 https://scifaro.com/en/abs/ara2-exploring-single-and-multi-core-vector-processing-with-an-efficient-rvv-1-0-compliant-open-source-processor-2311.074932024-06-18 https://scifaro.com/en/abs/epim-efficient-processing-in-memory-accelerators-based-on-epitome-2311.076202024-04-18 https://scifaro.com/en/abs/a-high-frequency-load-store-queue-with-speculative-allocations-for-high-level-synthesis-2311.081982023-11-15 https://scifaro.com/en/abs/cv32rt-enabling-fast-interrupt-and-context-switching-for-risc-v-microcontrollers-2311.083202023-11-15 https://scifaro.com/en/abs/masterrtl-a-pre-synthesis-ppa-estimation-framework-for-any-rtl-design-2311.084412023-11-16 https://scifaro.com/en/abs/comet-a-cross-layer-optimized-optical-phase-change-main-memory-architecture-2311.085662023-11-16 https://scifaro.com/en/abs/dreamplacefpga-mp-an-open-source-gpu-accelerated-macro-placer-for-modern-fpgas-with-cascade-shapes-and-region-constraints-2311.085822023-11-16 https://scifaro.com/en/abs/real-time-adaptive-neural-network-on-fpga-enhancing-adaptability-through-dynamic-classifier-selection-2311.095162024-08-28 https://scifaro.com/en/abs/pels-a-lightweight-and-flexible-peripheral-event-linking-system-for-ultra-low-power-iot-processors-2311.096452024-01-19 https://scifaro.com/en/abs/axi-realm-a-lightweight-and-modular-interconnect-extension-for-traffic-regulation-and-monitoring-of-heterogeneous-real-time-socs-2311.096622023-11-17 https://scifaro.com/en/abs/mega-a-memory-efficient-gnn-accelerator-exploiting-degree-aware-mixed-precision-quantization-2311.097752023-11-17 https://scifaro.com/en/abs/stella-nera-a-differentiable-maddness-based-hardware-accelerator-for-efficient-approximate-matrix-multiplication-2311.102072025-07-28 https://scifaro.com/en/abs/improving-fsm-state-enumeration-performance-for-hardware-security-with-recut-and-refsm-sat-2311.102732023-11-20 https://scifaro.com/en/abs/near-memory-parallel-indexing-and-coalescing-enabling-highly-efficient-indirect-access-for-spmv-2311.103782023-11-20 https://scifaro.com/en/abs/reusesense-with-great-reuse-comes-greater-efficiency-effectively-employing-computation-reuse-on-general-purpose-cpus-2311.104872023-11-20 https://scifaro.com/en/abs/luna-cim-lookup-table-based-programmable-neural-processing-in-memory-2311.105812023-11-20 https://scifaro.com/en/abs/uhd-unary-processing-for-lightweight-and-dynamic-hyperdimensional-computing-2311.107782023-11-21 https://scifaro.com/en/abs/power-aware-scheduling-of-tasks-on-fpgas-in-data-centers-2311.110152023-11-21 https://scifaro.com/en/abs/pimsab-a-processing-in-memory-system-with-spatially-aware-communication-and-bit-serial-aware-computation-2311.113842023-11-21 https://scifaro.com/en/abs/fast-inner-product-algorithms-and-architectures-for-deep-neural-network-accelerators-2311.122242023-11-22 https://scifaro.com/en/abs/wireless-bms-architecture-for-secure-readout-in-vehicle-and-second-life-applications-2311.122262023-11-22 https://scifaro.com/en/abs/improvements-in-interlayer-pipelining-of-cnn-accelerators-using-genetic-algorithms-2311.122352023-11-22 https://scifaro.com/en/abs/greenfpga-evaluating-fpgas-as-environmentally-sustainable-computing-solutions-2311.123962024-07-10 https://scifaro.com/en/abs/metastore-high-performance-metagenomic-analysis-via-in-storage-computing-2311.125272023-11-22 https://scifaro.com/en/abs/hyft-a-reconfigurable-softmax-accelerator-with-hybrid-numeric-format-for-both-training-and-inference-2311.132902024-09-05 https://scifaro.com/en/abs/systemc-model-of-power-side-channel-attacks-against-ai-accelerators-superstition-or-not-2311.133872024-12-11 https://scifaro.com/en/abs/soniq-system-optimized-noise-injected-ultra-low-precision-quantization-with-full-precision-parity-2311.141142025-11-11 https://scifaro.com/en/abs/anysyn-a-cost-generic-logic-synthesis-framework-with-customizable-cost-functions-2311.147212023-12-01 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https://scifaro.com/en/abs/llm4eda-emerging-progress-in-large-language-models-for-electronic-design-automation-2401.122242024-01-24 https://scifaro.com/en/abs/a-lightweight-fpga-based-ids-ecu-architecture-for-automotive-can-2401.122342024-01-24 https://scifaro.com/en/abs/acs-concurrent-kernel-execution-on-irregular-input-dependent-computational-graphs-2401.123772024-01-24 https://scifaro.com/en/abs/cim-mlc-a-multi-level-compilation-stack-for-computing-in-memory-accelerators-2401.124282024-05-09 https://scifaro.com/en/abs/full-stack-optimization-for-cam-only-dnn-inference-2401.126302024-01-24 https://scifaro.com/en/abs/a-modular-architecture-for-imu-based-data-gloves-2401.132542024-01-25 https://scifaro.com/en/abs/specllm-exploring-generation-and-review-of-vlsi-design-specification-with-large-language-model-2401.132662024-01-25 https://scifaro.com/en/abs/the-landscape-of-compute-near-memory-and-compute-in-memory-a-research-and-commercial-overview-2401.144282024-01-29 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https://scifaro.com/en/abs/makinote-an-fpga-based-hw-sw-platform-for-pre-silicon-emulation-of-risc-v-designs-2401.179842024-02-06 https://scifaro.com/en/abs/using-the-abstract-computer-architecture-description-language-to-model-ai-hardware-accelerators-2402.000692024-02-02 https://scifaro.com/en/abs/assertllm-generating-and-evaluating-hardware-verification-assertions-from-design-specifications-via-multi-llms-2402.003862026-02-26 https://scifaro.com/en/abs/one-sa-enabling-nonlinear-operations-in-systolic-arrays-for-efficient-and-flexible-neural-network-inference-2402.003952024-02-02 https://scifaro.com/en/abs/optimization-of-a-line-detection-algorithm-for-autonomous-vehicles-on-a-risc-v-with-accelerator-2402.004962024-02-02 https://scifaro.com/en/abs/reuse-detector-improving-the-management-of-stt-ram-sllcs-2402.005332024-02-02 https://scifaro.com/en/abs/cocco-hardware-mapping-co-exploration-towards-memory-capacity-communication-optimization-2402.006292024-02-02 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https://scifaro.com/en/abs/algorithm-hardware-co-design-for-energy-efficient-a-d-conversion-in-reram-based-accelerators-2402.061642024-03-11 https://scifaro.com/en/abs/pulse-parametric-hardware-units-for-low-power-sparsity-aware-convolution-engine-2402.062102024-02-12 https://scifaro.com/en/abs/a-precision-optimized-fixed-point-near-memory-digital-processing-unit-for-analog-in-memory-computing-2402.075492024-07-10 https://scifaro.com/en/abs/lfoc-a-fair-os-level-cache-clustering-policy-for-commodity-multicore-systems-2402.076932024-02-13 https://scifaro.com/en/abs/ir-aware-eco-timing-optimization-using-reinforcement-learning-2402.077812024-10-08 https://scifaro.com/en/abs/stochastic-spiking-attention-accelerating-attention-with-stochastic-computing-in-spiking-networks-2402.091092024-11-12 https://scifaro.com/en/abs/reusing-softmax-hardware-unit-for-gelu-computation-in-transformers-2402.101182024-02-19 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https://scifaro.com/en/abs/a-low-dissipation-and-scalable-gemm-accelerator-with-silicon-nitride-photonics-2402.110472024-02-20 https://scifaro.com/en/abs/variability-aware-noise-induced-dynamic-instability-of-ultra-low-voltage-sram-bitcells-2402.116852024-02-20 https://scifaro.com/en/abs/stochastic-nonlinear-dynamical-modelling-of-sram-bitcells-in-retention-mode-2402.116912024-02-20 https://scifaro.com/en/abs/cimnet-towards-joint-optimization-for-dnn-architecture-and-configuration-for-compute-in-memory-hardware-2402.117802024-03-19 https://scifaro.com/en/abs/factor-machine-mixed-signal-architecture-for-fine-grained-graph-based-computing-2402.121302024-02-21 https://scifaro.com/en/abs/a-system-development-kit-for-big-data-applications-on-fpga-based-clusters-the-everest-approach-2402.126122024-02-21 https://scifaro.com/en/abs/ddc-a-vision-for-a-disaggregated-datacenter-2402.127422024-02-21 https://scifaro.com/en/abs/sat-based-exact-modulo-scheduling-mapping-for-resource-constrained-cgras-2402.128342024-05-30 https://scifaro.com/en/abs/enabling-efficient-hybrid-systolic-computation-in-shared-l1-memory-manycore-clusters-2402.129862024-04-25 https://scifaro.com/en/abs/benchmarking-and-dissecting-the-nvidia-hopper-gpu-architecture-2402.134992024-02-22 https://scifaro.com/en/abs/guac-energy-aware-and-ssa-based-generation-of-coarse-grained-merged-accelerators-from-llvm-ir-2402.135132024-02-22 https://scifaro.com/en/abs/modsram-algorithm-hardware-co-design-for-large-number-modular-multiplication-in-sram-2402.141522024-02-23 https://scifaro.com/en/abs/an-fpga-based-accelerator-enabling-efficient-support-for-cnns-with-arbitrary-kernel-sizes-2402.143072024-02-23 https://scifaro.com/en/abs/thermal-aware-floorplanner-for-3d-ic-including-tsvs-liquid-microchannels-and-thermal-domains-optimization-2402.146272024-02-23 https://scifaro.com/en/abs/toward-high-performance-programmable-extreme-edge-intelligence-for-neuromorphic-vision-sensors-utilizing-magnetic-domain-wall-motion-based-mtj-2402.151212024-02-26 https://scifaro.com/en/abs/trimma-trimming-metadata-storage-and-latency-for-hybrid-memory-systems-2402.163432024-08-27 https://scifaro.com/en/abs/pygim-an-efficient-graph-neural-network-library-for-real-processing-in-memory-architectures-2402.167312025-04-08 https://scifaro.com/en/abs/ssresf-sensitivity-aware-single-particle-radiation-effects-simulation-framework-in-soc-platforms-based-on-svm-algorithm-2402.174892024-02-29 https://scifaro.com/en/abs/a-hierarchical-dataflow-driven-heterogeneous-architecture-for-wireless-baseband-processing-2402.180702025-06-23 https://scifaro.com/en/abs/pimsim-nn-an-isa-based-simulation-framework-for-processing-in-memory-accelerators-2402.180892024-02-29 https://scifaro.com/en/abs/pimsyn-synthesizing-processing-in-memory-cnn-accelerators-2402.181142024-02-29 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https://scifaro.com/en/abs/commercial-evaluation-of-zero-skipping-mac-design-for-bit-sparsity-exploitation-in-dl-inference-2402.193762025-01-03 https://scifaro.com/en/abs/fttn-feature-targeted-testing-for-numerical-properties-of-nvidia-amd-matrix-accelerators-2403.002322024-03-04 https://scifaro.com/en/abs/neupims-npu-pim-heterogeneous-acceleration-for-batched-llm-inferencing-2403.005792024-06-21 https://scifaro.com/en/abs/towards-fair-and-firm-real-time-scheduling-in-dnn-multi-tenant-multi-accelerator-systems-via-reinforcement-learning-2403.007662024-03-05 https://scifaro.com/en/abs/neuralut-hiding-neural-network-density-in-boolean-synthesizable-functions-2403.008492024-12-10 https://scifaro.com/en/abs/performance-evaluation-of-acceleration-of-convolutional-layers-on-openedgecgra-2403.012362024-03-05 https://scifaro.com/en/abs/efficient-fir-filtering-with-bit-layer-multiply-accumulator-2403.013512024-03-05 https://scifaro.com/en/abs/camasim-a-comprehensive-simulation-framework-for-content-addressable-memory-based-accelerators-2403.034422024-03-11 https://scifaro.com/en/abs/silicon-photonic-2-5d-interposer-networks-for-overcoming-communication-bottlenecks-in-scale-out-machine-learning-hardware-accelerators-2403.041892024-03-08 https://scifaro.com/en/abs/a-methodology-to-automatically-optimize-dynamic-memory-managers-applying-grammatical-evolution-2403.044142024-03-08 https://scifaro.com/en/abs/puma-efficient-and-low-cost-memory-allocation-and-alignment-support-for-processing-using-memory-architectures-2403.045392024-03-08 https://scifaro.com/en/abs/virtuoso-enabling-fast-and-accurate-virtual-memory-research-via-an-imitation-based-operating-system-simulation-methodology-2403.046352025-03-28 https://scifaro.com/en/abs/a-28-6-mj-iter-stable-diffusion-processor-for-text-to-image-generation-with-patch-similarity-based-sparsity-augmentation-and-text-based-mixed-precision-2403.049822024-09-24 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https://scifaro.com/en/abs/the-dawn-of-ai-native-eda-opportunities-and-challenges-of-large-circuit-models-2403.072572025-04-18 https://scifaro.com/en/abs/performance-analysis-of-matrix-multiplication-for-deep-learning-on-the-edge-2403.077312024-03-13 https://scifaro.com/en/abs/flexnn-a-dataflow-aware-flexible-deep-learning-accelerator-for-energy-efficient-edge-devices-2403.090262025-06-27 https://scifaro.com/en/abs/analytical-heterogeneous-die-to-die-3d-placement-with-macros-2403.090702024-08-14 https://scifaro.com/en/abs/bandwidth-effective-dram-cache-for-gpus-with-storage-class-memory-2403.093582024-03-15 https://scifaro.com/en/abs/matador-automated-system-on-chip-tsetlin-machine-design-generation-for-edge-applications-2403.105382024-03-19 https://scifaro.com/en/abs/a-hybrid-delay-model-for-interconnected-multi-input-gates-2403.105402025-02-25 https://scifaro.com/en/abs/sf-mmcn-low-power-sever-flow-multi-mode-diffusion-model-accelerator-2403.105422024-09-27 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https://scifaro.com/en/abs/hcim-adc-less-hybrid-analog-digital-compute-in-memory-accelerator-for-deep-learning-workloads-2403.135772024-03-21 https://scifaro.com/en/abs/e-syn-e-graph-rewriting-with-technology-aware-cost-functions-for-logic-synthesis-2403.142422024-04-02 https://scifaro.com/en/abs/dacapo-accelerating-continuous-learning-in-autonomous-systems-for-video-analytics-2403.143532024-08-16 https://scifaro.com/en/abs/beehive-a-flexible-network-stack-for-direct-attached-accelerators-2403.147702025-07-15 https://scifaro.com/en/abs/allspark-workload-orchestration-for-visual-transformers-on-processing-in-memory-systems-2403.150692024-09-20 https://scifaro.com/en/abs/a-two-level-neural-approach-combining-off-chip-prediction-with-adaptive-prefetch-filtering-2403.151812025-11-04 https://scifaro.com/en/abs/thermal-analysis-for-nvidia-gtx480-fermi-gpu-architecture-2403.162392024-03-26 https://scifaro.com/en/abs/electron-tunnelling-noise-programmable-random-variate-accelerator-for-monte-carlo-sampling-2403.164212024-04-09 https://scifaro.com/en/abs/partially-precise-computing-paradigm-for-efficient-hardware-implementation-of-application-specific-embedded-systems-2403.165772024-03-26 https://scifaro.com/en/abs/sip-autotuning-gpu-native-schedules-via-stochastic-instruction-perturbation-2403.168632024-03-26 https://scifaro.com/en/abs/merits-of-time-domain-computing-for-vmm-a-quantitative-comparison-2403.183672024-05-22 https://scifaro.com/en/abs/annotating-slack-directly-on-your-verilog-fine-grained-rtl-timing-evaluation-for-early-optimization-2403.184532024-05-07 https://scifaro.com/en/abs/neomem-hardware-software-co-design-for-cxl-native-memory-tiering-2403.187022024-09-12 https://scifaro.com/en/abs/testing-resource-isolation-for-system-on-chip-architectures-2403.187202024-03-28 https://scifaro.com/en/abs/smof-streaming-modern-cnns-on-fpgas-with-smart-off-chip-eviction-2403.189212024-03-29 https://scifaro.com/en/abs/dataflow-aware-pim-enabled-manycore-architecture-for-deep-learning-workloads-2403.190732024-03-29 https://scifaro.com/en/abs/hot-lego-architect-microfluidic-cooling-equipped-3dics-with-pre-rtl-thermal-simulation-2403.200502024-04-01 https://scifaro.com/en/abs/an-fpga-based-reconfigurable-accelerator-for-convolution-transformer-hybrid-efficientvit-2403.202302024-04-01 https://scifaro.com/en/abs/balanced-data-placement-for-gemv-acceleration-with-processing-in-memory-2403.202972024-04-02 https://scifaro.com/en/abs/rl-mul-2-0-multiplier-design-optimization-with-parallel-deep-reinforcement-learning-and-space-reduction-2404.006392024-12-30 https://scifaro.com/en/abs/there-and-back-again-a-netlist-s-tale-with-much-egraphin-2404.007862024-04-02 https://scifaro.com/en/abs/analyzing-the-single-event-upset-vulnerability-of-binarized-neural-networks-on-sram-fpgas-2404.017572024-04-03 https://scifaro.com/en/abs/optimizing-offload-performance-in-heterogeneous-mpsocs-2404.019082025-11-11 https://scifaro.com/en/abs/a-fully-configurable-open-source-software-defined-digital-quantized-spiking-neural-core-architecture-2404.022482024-04-04 https://scifaro.com/en/abs/netsmith-an-optimization-framework-for-machine-discovered-network-topologies-2404.023572024-04-04 https://scifaro.com/en/abs/spin-neuromem-a-low-power-neuromorphic-associative-memory-design-based-on-spintronic-devices-2404.024632025-09-23 https://scifaro.com/en/abs/qed-scalable-verification-of-hardware-memory-consistency-2404.031132024-04-05 https://scifaro.com/en/abs/h3dfact-heterogeneous-3d-integrated-cim-for-factorization-with-holographic-perceptual-representations-2404.041732024-04-08 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https://scifaro.com/en/abs/wasp-warp-scheduling-to-mimic-prefetching-in-graphics-workloads-2404.061562024-04-10 https://scifaro.com/en/abs/modeling-analog-digital-converter-energy-and-area-for-compute-in-memory-accelerator-design-2404.065532024-05-15 https://scifaro.com/en/abs/pim-opt-demystifying-distributed-optimization-algorithms-on-a-real-world-processing-in-memory-system-2404.071642024-09-30 https://scifaro.com/en/abs/block-ssd-a-new-block-based-blocking-ssd-architecture-2404.072282024-04-12 https://scifaro.com/en/abs/llm-aided-explanations-of-eda-synthesis-errors-2404.072352024-10-21 https://scifaro.com/en/abs/on-reducing-the-execution-latency-of-superconducting-quantum-processors-via-quantum-job-scheduling-2404.078822025-05-05 https://scifaro.com/en/abs/modulo-2-2n-1-arithmetic-via-two-parallel-n-bit-residue-channels-2404.082282024-12-12 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https://scifaro.com/en/abs/understanding-the-performance-horizon-of-the-latest-ml-workloads-with-nongemm-workloads-2404.117882025-04-17 https://scifaro.com/en/abs/cicero-addressing-algorithmic-and-architectural-bottlenecks-in-neural-rendering-by-radiance-warping-and-memory-optimizations-2404.118522024-04-19 https://scifaro.com/en/abs/en-t-optimizing-tensor-computing-engines-performance-via-encoder-based-methodology-2404.118872024-10-24 https://scifaro.com/en/abs/switchable-single-dual-edge-registers-for-pipeline-architecture-2404.123062024-04-19 https://scifaro.com/en/abs/combining-power-and-arithmetic-optimization-via-datapath-rewriting-2404.123362024-04-19 https://scifaro.com/en/abs/strela-streaming-elastic-cgra-accelerator-for-embedded-systems-2404.125032024-04-22 https://scifaro.com/en/abs/dg-replace-a-dataflow-driven-gpu-accelerated-analytical-global-placement-framework-for-machine-learning-accelerators-2404.130492024-06-21 https://scifaro.com/en/abs/fpga-divide-and-conquer-placement-using-deep-reinforcement-learning-2404.130612024-04-23 https://scifaro.com/en/abs/easyacim-an-end-to-end-automated-analog-cim-with-synthesizable-architecture-and-agile-design-space-exploration-2404.130622024-04-23 https://scifaro.com/en/abs/a-stochastic-rounding-enabled-low-precision-floating-point-mac-for-dnn-training-2404.140102024-09-27 https://scifaro.com/en/abs/on-the-systematic-creation-of-faithfully-rounded-commutative-truncated-booth-multipliers-2404.140692024-04-23 https://scifaro.com/en/abs/tdram-tag-enhanced-dram-for-efficient-caching-2404.146172024-04-24 https://scifaro.com/en/abs/workload-aware-hardware-accelerator-mining-for-distributed-deep-learning-training-2404.146322024-04-24 https://scifaro.com/en/abs/a-high-level-synthesis-approach-for-precisely-timed-energy-efficient-embedded-systems-2404.147692024-04-24 https://scifaro.com/en/abs/pivot-input-aware-path-selection-for-energy-efficient-vit-inference-2404.151852024-04-24 https://scifaro.com/en/abs/neurachip-accelerating-gnn-computations-with-a-hash-based-decoupled-spatial-accelerator-2404.155102024-04-30 https://scifaro.com/en/abs/blisscam-boosting-eye-tracking-efficiency-with-learned-in-sensor-sparse-sampling-2404.157332024-04-25 https://scifaro.com/en/abs/apache-a-processing-near-memory-architecture-for-multi-scheme-fully-homomorphic-encryption-2404.158192024-12-16 https://scifaro.com/en/abs/a-configurable-and-efficient-memory-hierarchy-for-neural-network-hardware-accelerator-2404.158232024-04-25 https://scifaro.com/en/abs/the-feasibility-of-implementing-large-scale-transformers-on-multi-fpga-platforms-2404.161582024-04-26 https://scifaro.com/en/abs/flaash-flexible-accelerator-architecture-for-sparse-high-order-tensor-contraction-2404.163172024-04-26 https://scifaro.com/en/abs/implementing-and-optimizing-the-scaled-dot-product-attention-on-streaming-dataflow-2404.166292024-08-09 https://scifaro.com/en/abs/record-acceleration-of-the-two-dimensional-ising-model-using-high-performance-wafer-scale-engine-2404.169902024-05-03 https://scifaro.com/en/abs/embedded-fpga-developments-in-130nm-and-28nm-cmos-for-machine-learning-in-particle-detector-readout-2404.177012024-08-29 https://scifaro.com/en/abs/time-reversal-for-near-field-communications-on-multi-chip-wireless-networks-2404.185622024-05-01 https://scifaro.com/en/abs/maco-exploring-gemm-acceleration-on-a-loosely-coupled-multi-core-processor-2404.191802024-05-01 https://scifaro.com/en/abs/pefsl-a-deployment-pipeline-for-embedded-few-shot-learning-on-a-fpga-soc-2404.193542024-06-27 https://scifaro.com/en/abs/low-overhead-general-purpose-near-data-processing-in-cxl-memory-expanders-2404.193812024-10-07 https://scifaro.com/en/abs/selective-parallel-loading-of-large-scale-compressed-graphs-with-paragrapher-2404.197352025-10-29 https://scifaro.com/en/abs/hardware-accelerators-for-autonomous-cars-a-review-2405.000622024-05-02 https://scifaro.com/en/abs/hlstransform-energy-efficient-llama-2-inference-on-fpgas-via-high-level-synthesis-2405.007382024-05-03 https://scifaro.com/en/abs/scar-scheduling-multi-model-ai-workloads-on-heterogeneous-multi-chiplet-module-accelerators-2405.007902024-09-17 https://scifaro.com/en/abs/hlsfactory-a-framework-empowering-high-level-synthesis-datasets-for-machine-learning-and-beyond-2405.008202025-10-27 https://scifaro.com/en/abs/natural-language-to-verilog-design-of-a-recurrent-spiking-neural-network-using-large-language-models-and-chatgpt-2405.014192024-12-12 https://scifaro.com/en/abs/pipeorgan-efficient-inter-operation-pipelining-with-flexible-spatial-organization-and-interconnects-2405.017362024-05-06 https://scifaro.com/en/abs/torch2chip-an-end-to-end-customizable-deep-neural-network-compression-and-deployment-toolkit-for-prototype-hardware-accelerator-design-2405.017752024-05-07 https://scifaro.com/en/abs/towards-sustainable-low-carbon-emission-mini-data-centres-2405.019092024-05-16 https://scifaro.com/en/abs/small-logic-based-multipliers-with-incomplete-sub-multipliers-for-fpgas-2405.020472024-05-06 https://scifaro.com/en/abs/transimpedance-amplifier-with-automatic-gain-control-based-on-memristors-for-optical-signal-acquisition-2405.021692024-05-06 https://scifaro.com/en/abs/gta-a-new-general-tensor-accelerator-with-better-area-efficiency-and-data-reuse-2405.021962024-05-06 https://scifaro.com/en/abs/cnn-based-equalization-for-communications-achieving-gigabit-throughput-with-a-flexible-fpga-hardware-architecture-2405.023232024-05-07 https://scifaro.com/en/abs/evaluating-llms-for-hardware-design-and-test-2405.023262024-12-03 https://scifaro.com/en/abs/digital-asic-design-with-ongoing-llms-strategies-and-prospects-2405.023292024-05-07 https://scifaro.com/en/abs/efficient-open-modification-spectral-library-searching-in-high-dimensional-space-with-multi-level-cell-memory-2405.027562024-11-15 https://scifaro.com/en/abs/basilisk-achieving-competitive-performance-with-open-eda-tools-on-an-open-source-linux-capable-risc-v-soc-2405.035232024-05-07 https://scifaro.com/en/abs/deltakws-a-65nm-36nj-decision-bio-inspired-temporal-sparsity-aware-digital-keyword-spotting-ic-with-0-6v-near-threshold-sram-2405.039052024-11-27 https://scifaro.com/en/abs/nova-noc-based-vector-unit-for-mapping-attention-layers-on-a-cnn-accelerator-2405.042062024-05-08 https://scifaro.com/en/abs/insights-from-basilisk-are-open-source-eda-tools-ready-for-a-multi-million-gate-linux-booting-rv64-soc-design-2405.042572024-05-09 https://scifaro.com/en/abs/floorset-a-vlsi-floorplanning-dataset-with-design-constraints-of-real-world-socs-2405.054802024-08-05 https://scifaro.com/en/abs/simultaneous-many-row-activation-in-off-the-shelf-dram-chips-experimental-characterization-and-analysis-2405.060812024-05-13 https://scifaro.com/en/abs/meic-re-thinking-rtl-debug-automation-using-llms-2405.068402024-05-14 https://scifaro.com/en/abs/cimloop-a-flexible-accurate-and-fast-compute-in-memory-modeling-tool-2405.072592024-11-01 https://scifaro.com/en/abs/sambanova-sn40l-scaling-the-ai-memory-wall-with-dataflow-and-composition-of-experts-2405.075182024-11-06 https://scifaro.com/en/abs/a-mess-of-memory-system-benchmarking-simulation-and-application-profiling-2405.101702024-12-10 https://scifaro.com/en/abs/lean-attention-hardware-aware-scalable-attention-mechanism-for-the-decode-phase-of-transformers-2405.104802025-01-15 https://scifaro.com/en/abs/nertcam-cam-based-cmos-implementation-of-reference-frames-for-neuromorphic-processors-2405.118442024-05-21 https://scifaro.com/en/abs/using-formal-verification-to-evaluate-single-event-upsets-in-a-risc-v-core-2405.120892024-05-21 https://scifaro.com/en/abs/automatic-hardware-pragma-insertion-in-high-level-synthesis-a-non-linear-programming-approach-2405.123042025-02-11 https://scifaro.com/en/abs/adaptive-robotic-arm-control-with-a-spiking-recurrent-neural-network-on-a-digital-accelerator-2405.128492024-06-04 https://scifaro.com/en/abs/feather-a-reconfigurable-accelerator-with-data-reordering-support-for-low-cost-on-chip-dataflow-switching-2405.131702026-04-07 https://scifaro.com/en/abs/full-stack-evaluation-of-machine-learning-inference-workloads-for-risc-v-systems-2405.153802024-05-27 https://scifaro.com/en/abs/single-event-upset-analysis-of-a-systolic-array-based-deep-neural-network-accelerator-2405.153812024-05-27 https://scifaro.com/en/abs/sums-sniffing-unknown-multiband-signals-under-low-sampling-rates-2405.157052024-05-27 https://scifaro.com/en/abs/swat-scalable-and-efficient-window-attention-based-transformers-acceleration-on-fpgas-2405.170252024-05-28 https://scifaro.com/en/abs/optimized-thread-block-arrangement-in-a-gpu-implementation-of-a-linear-solver-for-atmospheric-chemistry-mechanisms-2405.173632024-05-28 https://scifaro.com/en/abs/dr-cgra-supporting-loop-carried-dependencies-in-cgras-without-spilling-intermediate-values-2405.173652024-05-28 https://scifaro.com/en/abs/enthuse-efficient-adaptable-high-throughput-streaming-aggregation-engines-2405.181682026-01-05 https://scifaro.com/en/abs/xtern-energy-efficient-ternary-neural-network-inference-on-risc-v-based-edge-systems-2405.190652024-05-30 https://scifaro.com/en/abs/chiplets-on-wheels-review-paper-on-holistic-chiplet-solutions-for-autonomous-vehicles-2406.001822024-06-04 https://scifaro.com/en/abs/l2r-cipu-efficient-cnn-computation-with-left-to-right-composite-inner-product-units-2406.003602024-07-10 https://scifaro.com/en/abs/an-automated-validation-framework-for-power-management-and-data-retention-logic-kits-of-standard-cell-library-2406.005422024-06-04 https://scifaro.com/en/abs/designing-reconfigurable-interconnection-network-of-heterogeneous-chiplets-using-kalman-filter-2406.005682024-06-04 https://scifaro.com/en/abs/chiplet-gym-optimizing-chiplet-based-ai-accelerator-design-with-reinforcement-learning-2406.008582024-06-04 https://scifaro.com/en/abs/ade-hgnn-accelerating-hgnns-through-attention-disparity-exploitation-2406.009882024-06-04 https://scifaro.com/en/abs/a-0-96pj-sop-30-23k-neuron-mm-2-heterogeneous-neuromorphic-chip-with-fullerene-like-interconnection-topology-for-edge-ai-computing-2406.011512024-06-04 https://scifaro.com/en/abs/demystifying-ai-platform-design-for-distributed-inference-of-next-generation-llm-models-2406.016982025-05-16 https://scifaro.com/en/abs/lmb-augmenting-pcie-devices-with-cxl-linked-memory-buffer-2406.020392024-06-05 https://scifaro.com/en/abs/fast-and-practical-strassen-s-matrix-multiplication-using-fpgas-2406.020882024-06-05 https://scifaro.com/en/abs/hass-hardware-aware-sparsity-search-for-dataflow-dnn-accelerator-2406.030882024-06-06 https://scifaro.com/en/abs/soft-gpgpu-versus-ip-cores-quantifying-and-reducing-the-performance-gap-2406.032272024-06-06 https://scifaro.com/en/abs/llumnix-dynamic-scheduling-for-large-language-model-serving-2406.032432024-06-07 https://scifaro.com/en/abs/a-2-5-na-area-efficient-temperature-independent-176-82-ppm-deg-c-cmos-only-current-reference-in-0-11-mu-m-bulk-and-22-nm-fd-soi-2406.047412024-11-13 https://scifaro.com/en/abs/mexican-computers-a-brief-technical-and-historical-overview-2406.049122024-06-12 https://scifaro.com/en/abs/look-up-table-based-neural-network-hardware-2406.052822024-10-02 https://scifaro.com/en/abs/investigating-memory-failure-prediction-across-cpu-architectures-2406.053542024-12-17 https://scifaro.com/en/abs/highly-versatile-fpga-implemented-cyber-coherent-ising-machine-2406.053772024-12-10 https://scifaro.com/en/abs/evaluation-of-posits-for-spectral-analysis-using-a-software-defined-dataflow-architecture-2406.053982024-06-11 https://scifaro.com/en/abs/fsead-a-composable-fpga-based-streaming-ensemble-anomaly-detection-library-2406.059992024-06-11 https://scifaro.com/en/abs/a-gigabit-dma-enhanced-open-source-ethernet-controller-for-mixed-criticality-systems-2406.063942024-06-11 https://scifaro.com/en/abs/pragmatic-formal-verification-methodology-for-clock-domain-crossing-cdc-2406.065332024-06-12 https://scifaro.com/en/abs/apparate-evading-memory-hierarchy-with-godspeed-wireless-on-chip-2406.065362024-06-12 https://scifaro.com/en/abs/global-and-local-attention-based-inception-u-net-for-static-ir-drop-prediction-2406.065412024-11-19 https://scifaro.com/en/abs/vmcu-coordinated-memory-management-and-kernel-optimization-for-dnn-inference-on-mcus-2406.065422024-06-12 https://scifaro.com/en/abs/sparrowsnn-a-hardware-software-co-design-for-energy-efficient-ecg-classification-2406.065432026-04-21 https://scifaro.com/en/abs/tsb-tiny-shared-block-for-efficient-dnn-deployment-on-nvcim-accelerators-2406.065442024-08-23 https://scifaro.com/en/abs/sentrycore-a-risc-v-co-processor-system-for-safe-real-time-control-applications-2406.065462024-06-12 https://scifaro.com/en/abs/large-language-model-llm-for-standard-cell-layout-design-optimization-2406.065492024-06-12 https://scifaro.com/en/abs/chibench-a-benchmark-suite-for-testing-electronic-design-automation-tools-2406.065502024-06-12 https://scifaro.com/en/abs/improving-instruction-fetch-efficiency-via-high-level-program-map-traversal-2406.067382026-04-02 https://scifaro.com/en/abs/hardware-implementation-of-soft-mapper-demappers-in-iterative-ep-based-receivers-2406.079342024-06-13 https://scifaro.com/en/abs/onnxim-a-fast-cycle-level-multi-core-npu-simulator-2406.080512024-06-13 https://scifaro.com/en/abs/continuous-time-digital-twin-with-analogue-memristive-neural-ordinary-differential-equation-solver-2406.083432024-06-13 https://scifaro.com/en/abs/memory-is-all-you-need-an-overview-of-compute-in-memory-architectures-for-accelerating-large-language-model-inference-2406.084132024-06-13 https://scifaro.com/en/abs/onnx-to-hardware-design-flow-for-adaptive-neural-network-inference-on-fpgas-2406.090782024-06-14 https://scifaro.com/en/abs/a-na-range-area-efficient-sub-100-ppm-deg-c-peaking-current-reference-using-forward-body-biasing-in-0-11-mu-m-bulk-and-22-nm-fd-soi-2406.091042024-06-14 https://scifaro.com/en/abs/python-based-dsl-for-generating-verilog-model-of-synchronous-digital-circuits-2406.092082024-06-14 https://scifaro.com/en/abs/c2hlsc-can-llms-bridge-the-software-to-hardware-design-gap-2406.092332025-04-15 https://scifaro.com/en/abs/optimizing-layer-fused-scheduling-of-transformer-networks-on-multi-accelerator-platforms-2406.098042024-06-17 https://scifaro.com/en/abs/fusemax-leveraging-extended-einsums-to-optimize-attention-accelerator-design-2406.104912026-01-28 https://scifaro.com/en/abs/triangel-a-high-performance-accurate-timely-on-chip-temporal-prefetcher-2406.106272024-10-18 https://scifaro.com/en/abs/towards-the-certification-of-hybrid-architectures-analysing-interference-on-hardware-accelerators-through-pml-2406.123462024-06-19 https://scifaro.com/en/abs/fast-graph-vector-search-via-hardware-acceleration-and-delayed-synchronization-traversal-2406.123852025-07-21 https://scifaro.com/en/abs/rover-rtl-optimization-via-verified-e-graph-rewriting-2406.124212024-06-19 https://scifaro.com/en/abs/an-experimental-characterization-of-combined-rowhammer-and-rowpress-read-disturbance-in-modern-dram-chips-2406.130802024-06-25 https://scifaro.com/en/abs/demonstration-of-low-power-and-highly-uniform-6-bit-operation-in-sio2-based-memristors-embedded-with-pt-nanoparticles-2406.135052024-06-21 https://scifaro.com/en/abs/amc-access-to-miss-correlation-prefetcher-for-evolving-graph-analytics-2406.140082024-06-21 https://scifaro.com/en/abs/cook-access-control-on-an-embedded-volta-gpu-2406.140812024-06-21 https://scifaro.com/en/abs/scalable-and-risc-v-programmable-near-memory-computing-architectures-for-edge-nodes-2406.142632025-03-28 https://scifaro.com/en/abs/presto-an-in-storage-data-preprocessing-system-for-training-recommendation-models-2406.145712024-06-24 https://scifaro.com/en/abs/cmds-cross-layer-dataflow-optimization-for-dnn-accelerators-exploiting-multi-bank-memories-2406.145742024-06-24 https://scifaro.com/en/abs/exploring-dram-cache-prefetching-for-pooled-memory-2406.147782024-06-24 https://scifaro.com/en/abs/risc-v-processor-enhanced-with-a-dynamic-micro-decoder-unit-2406.149992024-06-24 https://scifaro.com/en/abs/occamy-a-432-core-28-1-dp-gflop-s-w-83-fpu-utilization-dual-chiplet-dual-hbm2e-risc-v-based-accelerator-for-stencil-and-sparse-linear-algebra-computations-with-8-to-64-bit-floating-point-support-in-12nm-finfet-2406.150682024-06-24 https://scifaro.com/en/abs/basilisk-an-end-to-end-open-source-linux-capable-risc-v-soc-in-130nm-cmos-2406.151072024-06-24 https://scifaro.com/en/abs/rowpress-vulnerability-in-modern-dram-chips-2406.161532024-08-21 https://scifaro.com/en/abs/llm-aided-testbench-generation-and-bug-detection-for-finite-state-machines-2406.171322025-06-24 https://scifaro.com/en/abs/benchmarking-deep-learning-models-on-nvidia-jetson-nano-for-real-time-systems-an-empirical-investigation-2406.177492024-06-26 https://scifaro.com/en/abs/hypervisor-extension-for-a-risc-v-processor-2406.177962024-06-27 https://scifaro.com/en/abs/high-resolution-multi-channel-fpga-based-time-to-digital-converter-2406.177982024-06-27 https://scifaro.com/en/abs/design-implementation-and-evaluation-of-the-svnapot-extension-on-a-risc-v-processor-2406.178022024-06-27 https://scifaro.com/en/abs/nox-a-compact-open-source-risc-v-processor-for-multi-processor-systems-on-chip-2406.178782024-06-27 https://scifaro.com/en/abs/resilient-and-secure-programmable-system-on-chip-accelerator-offload-2406.181172024-06-27 https://scifaro.com/en/abs/a-jammer-mitigating-267-mb-s-3-78-mm-2-583-mw-32-times-8-multi-user-mimo-receiver-in-22fdx-2406.181492024-06-27 https://scifaro.com/en/abs/a-lightweight-algorithm-for-classifying-ex-vivo-tissues-samples-2406.183722024-06-27 https://scifaro.com/en/abs/on-approximate-8-bit-floating-point-operations-using-integer-operations-2406.184412024-06-27 https://scifaro.com/en/abs/constable-improving-performance-and-power-efficiency-by-safely-eliminating-load-instruction-execution-2406.187862024-06-28 https://scifaro.com/en/abs/layoutcopilot-an-llm-powered-multi-agent-collaborative-framework-for-interactive-analog-layout-design-2406.188732025-01-14 https://scifaro.com/en/abs/megis-high-performance-energy-efficient-and-low-cost-metagenomic-analysis-with-in-storage-processing-2406.191132024-06-28 https://scifaro.com/en/abs/fred-flexible-reduction-distribution-interconnect-and-communication-implementation-for-wafer-scale-distributed-training-of-dnn-models-2406.195802025-06-10 https://scifaro.com/en/abs/cis-composable-instruction-set-for-data-streaming-applications-2407.002072025-04-29 https://scifaro.com/en/abs/fast-overlapim-a-fast-overlap-driven-mapping-framework-for-processing-in-memory-neural-network-acceleration-2407.006042024-07-02 https://scifaro.com/en/abs/multi-objective-optimization-for-common-centroid-placement-of-analog-transistors-2407.008172025-04-18 https://scifaro.com/en/abs/exploring-fpga-designs-for-mx-and-beyond-2407.014752024-07-02 https://scifaro.com/en/abs/theseus-exploring-efficient-wafer-scale-chip-design-for-large-language-models-2407.020792024-11-25 https://scifaro.com/en/abs/fast-scalable-energy-efficient-non-element-wise-matrix-multiplication-on-fpga-2407.023622024-07-09 https://scifaro.com/en/abs/risc-v-r-extension-advancing-efficiency-with-rented-pipeline-for-edge-dnn-processing-2407.026222024-07-04 https://scifaro.com/en/abs/control-flow-management-in-modern-gpus-2407.029442024-07-04 https://scifaro.com/en/abs/a-95-5gb-s-29-6ns-worst-case-latency-orbgrand-decoder-for-6g-xurllc-2407.034972024-07-08 https://scifaro.com/en/abs/decoupled-access-execute-enabled-dvfs-for-tinyml-deployments-on-stm32-microcontrollers-2407.037112024-07-08 https://scifaro.com/en/abs/multiplier-design-addressing-area-delay-trade-offs-by-using-dsp-and-logic-resources-on-fpgas-2407.039622024-07-08 https://scifaro.com/en/abs/towards-generalized-on-chip-communication-for-programmable-accelerators-in-heterogeneous-architectures-2407.041822024-07-08 https://scifaro.com/en/abs/dadu-corki-algorithm-architecture-co-design-for-embodied-ai-powered-robotic-manipulation-2407.042922025-06-10 https://scifaro.com/en/abs/fixed-and-movable-antenna-technology-for-6g-integrated-sensing-and-communication-2407.044042024-07-17 https://scifaro.com/en/abs/music-lite-efficient-music-using-approximate-computing-an-ofdm-radar-case-study-2407.048492024-12-05 https://scifaro.com/en/abs/spatzformer-an-efficient-reconfigurable-dual-core-risc-v-v-cluster-for-mixed-scalar-vector-workloads-2407.054472024-07-09 https://scifaro.com/en/abs/scatter-algorithm-circuit-co-sparse-photonic-accelerator-with-thermal-tolerant-power-efficient-in-situ-light-redistribution-2407.055102024-07-09 https://scifaro.com/en/abs/accelerating-mri-uncertainty-estimation-with-mask-based-bayesian-neural-network-2407.055212024-07-09 https://scifaro.com/en/abs/ea4rca-efficient-aie-accelerator-design-framework-for-regular-communication-avoiding-algorithm-2407.056212024-07-10 https://scifaro.com/en/abs/hecaton-training-large-language-models-with-scalable-chiplet-systems-2407.057842024-11-28 https://scifaro.com/en/abs/kratos-an-fpga-benchmark-for-unrolled-dnns-with-fine-grained-sparsity-and-mixed-precision-2407.060332024-07-09 https://scifaro.com/en/abs/scaling-analog-photonic-accelerators-for-byte-size-integer-general-matrix-multiply-gemm-kernels-2407.061342024-07-09 https://scifaro.com/en/abs/studying-the-degradation-of-propagation-delay-on-fpgas-at-the-european-xfel-2407.066432024-07-10 https://scifaro.com/en/abs/laser-fault-injection-attacks-against-radiation-tolerant-tmr-registers-2407.067512024-07-10 https://scifaro.com/en/abs/a-46-gbps-12-pj-b-sparsity-adaptive-beamspace-equalizer-for-mmwave-massive-mimo-in-22fdx-2407.067552024-07-10 https://scifaro.com/en/abs/on-the-importance-of-reproducibility-of-experimental-results-especially-in-the-domain-of-security-2407.067602024-07-10 https://scifaro.com/en/abs/functional-type-expressions-of-sequential-circuits-with-the-notion-of-referring-forms-2407.081282025-01-22 https://scifaro.com/en/abs/opima-optical-processing-in-memory-for-convolutional-neural-network-acceleration-2407.082052024-07-12 https://scifaro.com/en/abs/natural-language-is-not-enough-benchmarking-multi-modal-generative-ai-for-verilog-generation-2407.084732024-07-12 https://scifaro.com/en/abs/flex-tpu-a-flexible-tpu-with-runtime-reconfigurable-dataflow-architecture-2407.087002024-07-12 https://scifaro.com/en/abs/deep-inverse-design-for-high-level-synthesis-2407.087972025-04-14 https://scifaro.com/en/abs/hybrid-temporal-computing-for-lower-power-hardware-accelerators-2407.089752024-07-15 https://scifaro.com/en/abs/dynamic-neural-network-with-memristive-cim-and-cam-for-2d-and-3d-vision-2407.089902024-07-15 https://scifaro.com/en/abs/imiv-in-memory-integrity-verification-for-nvm-2407.091802024-07-15 https://scifaro.com/en/abs/switch-less-dragonfly-on-wafers-a-scalable-interconnection-architecture-based-on-wafer-scale-integration-2407.102902024-08-27 https://scifaro.com/en/abs/effective-design-verification-constrained-random-with-python-and-cocotb-2407.103122024-07-16 https://scifaro.com/en/abs/towards-efficient-design-verification-constrained-random-verification-using-pyuvm-2407.103172024-07-16 https://scifaro.com/en/abs/sofa-a-compute-memory-optimized-sparsity-accelerator-via-cross-stage-coordinated-tiling-2407.104162024-07-16 https://scifaro.com/en/abs/assessing-the-performance-of-stateful-logic-in-1-selector-1-rram-crossbar-arrays-2407.104662024-07-16 https://scifaro.com/en/abs/approxpilot-a-gnn-based-accelerator-approximation-framework-2407.113242024-07-17 https://scifaro.com/en/abs/optimising-gpgpu-execution-through-runtime-micro-architecture-parameter-analysis-2407.119992024-07-18 https://scifaro.com/en/abs/idle-is-the-new-sleep-configuration-aware-alternative-to-powering-off-fpga-based-dl-accelerators-during-inactivity-2407.120272026-04-22 https://scifaro.com/en/abs/a-quality-aware-voltage-overscaling-framework-to-improve-the-energy-efficiency-and-lifetime-of-tpus-based-on-statistical-error-modeling-2407.120292024-07-18 https://scifaro.com/en/abs/a-novel-hdl-code-generator-for-effectively-testing-fpga-logic-synthesis-compilers-2407.120372024-07-18 https://scifaro.com/en/abs/rtl-verification-for-secure-speculation-using-contract-shadow-logic-2407.122322024-07-18 https://scifaro.com/en/abs/stox-net-stochastic-processing-of-partial-sums-for-efficient-in-memory-computing-dnn-accelerators-2407.123782024-11-11 https://scifaro.com/en/abs/sigdla-a-deep-learning-accelerator-extension-for-signal-processing-2407.125652024-07-18 https://scifaro.com/en/abs/graphitron-a-domain-specific-language-for-fpga-based-graph-processing-accelerator-generation-2407.125752024-07-18 https://scifaro.com/en/abs/iicpilot-an-intelligent-integrated-circuit-backend-design-framework-using-open-eda-2407.125762024-08-29 https://scifaro.com/en/abs/artemis-a-mixed-analog-stochastic-in-dram-accelerator-for-transformer-neural-networks-2407.126382024-07-18 https://scifaro.com/en/abs/pico-ram-a-pvt-insensitive-analog-compute-in-memory-sram-macro-with-in-situ-multi-bit-charge-computing-and-6t-thin-cell-compatible-layout-2407.128292024-07-19 https://scifaro.com/en/abs/loas-fully-temporal-parallel-dataflow-for-dual-sparse-spiking-neural-networks-2407.140732024-09-04 https://scifaro.com/en/abs/mixed-precision-neural-networks-on-risc-v-cores-isa-extensions-for-multi-pumped-soft-simd-operations-2407.142742024-08-14 https://scifaro.com/en/abs/performance-modeling-and-workload-analysis-of-distributed-large-language-model-training-and-inference-2407.146452024-07-23 https://scifaro.com/en/abs/benchmarking-end-to-end-performance-of-ai-based-chip-placement-algorithms-2407.150262024-12-09 https://scifaro.com/en/abs/token-picker-accelerating-attention-in-text-generation-with-minimized-memory-transfer-via-probability-estimation-2407.151312024-07-23 https://scifaro.com/en/abs/the-bicameral-cache-a-split-cache-for-vector-architectures-2407.154402025-03-28 https://scifaro.com/en/abs/kwt-tiny-risc-v-accelerated-embedded-keyword-spotting-transformer-2407.160262025-11-21 https://scifaro.com/en/abs/origen-enhancing-rtl-code-generation-with-code-to-code-augmentation-and-self-reflection-2407.162372024-09-04 https://scifaro.com/en/abs/the-magnificent-seven-challenges-and-opportunities-in-domain-specific-accelerator-design-for-autonomous-systems-2407.173112025-07-08 https://scifaro.com/en/abs/sky-epsilon-tree-embracing-the-batch-updates-of-b-epsilon-trees-through-access-port-parallelism-on-skyrmion-racetrack-memory-2407.174992024-07-26 https://scifaro.com/en/abs/an-energy-efficient-artefact-detection-accelerator-on-fpgas-for-hyper-spectral-satellite-imagery-2407.176472024-07-26 https://scifaro.com/en/abs/hg-pipe-vision-transformer-acceleration-with-hybrid-grained-pipeline-2407.178792024-08-02 https://scifaro.com/en/abs/maptune-advancing-asic-technology-mapping-via-reinforcement-learning-guided-library-tuning-2407.181102024-07-26 https://scifaro.com/en/abs/flexible-and-cost-effective-spherical-to-cartesian-coordinate-conversion-using-3-d-cordic-algorithm-on-fpga-2407.182552024-07-29 https://scifaro.com/en/abs/latency-optimized-deep-neural-networks-dnns-an-artificial-intelligence-approach-at-the-edge-using-multiprocessor-system-on-chip-mpsoc-2407.182642024-07-29 https://scifaro.com/en/abs/mcu-mixq-a-hw-sw-co-optimized-mixed-precision-neural-network-design-framework-for-mcus-2407.182672024-07-29 https://scifaro.com/en/abs/lamagic-language-model-based-topology-generation-for-analog-integrated-circuits-2407.182692024-08-30 https://scifaro.com/en/abs/large-language-model-for-verilog-generation-with-code-structure-guided-reinforcement-learning-2407.182712025-04-22 https://scifaro.com/en/abs/aicircuit-a-multi-level-dataset-and-benchmark-for-ai-driven-analog-integrated-circuit-design-2407.182722024-07-29 https://scifaro.com/en/abs/rome-was-not-built-in-a-single-step-hierarchical-prompting-for-llm-based-chip-design-2407.182762024-09-11 https://scifaro.com/en/abs/classification-based-automatic-hdl-code-generation-using-llms-2407.183262024-07-29 https://scifaro.com/en/abs/autovcoder-a-systematic-framework-for-automated-verilog-code-generation-using-llms-2407.183332024-07-29 https://scifaro.com/en/abs/non-overlapping-placement-of-macro-cells-based-on-reinforcement-learning-in-chip-design-2407.184992024-10-01 https://scifaro.com/en/abs/rose-opt-robust-and-efficient-analog-circuit-parameter-optimization-with-knowledge-infused-reinforcement-learning-2407.191502024-07-30 https://scifaro.com/en/abs/hennc-hardware-engine-for-artificial-neural-network-based-chaotic-oscillators-2407.191652024-07-30 https://scifaro.com/en/abs/obstacle-aware-length-matching-routing-for-any-direction-traces-in-printed-circuit-board-2407.191952024-07-30 https://scifaro.com/en/abs/a-high-throughput-fpga-accelerator-for-lightweight-cnns-with-balanced-dataflow-2407.194492024-12-17 https://scifaro.com/en/abs/evolutionary-approximation-of-ternary-neurons-for-on-sensor-printed-neural-networks-2407.205892024-07-31 https://scifaro.com/en/abs/configurable-multi-port-memory-architecture-for-high-speed-data-communication-2407.206282024-11-08 https://scifaro.com/en/abs/updown-programmable-fine-grained-events-for-scalable-performance-on-irregular-applications-2407.207732024-07-31 https://scifaro.com/en/abs/synthesis-of-resource-efficient-superconducting-circuits-with-clock-free-alternating-logic-2407.209422024-08-02 https://scifaro.com/en/abs/optical-computing-for-deep-neural-network-acceleration-foundations-recent-developments-and-emerging-directions-2407.211842024-08-01 https://scifaro.com/en/abs/functional-iss-driven-verification-of-superscalar-risc-v-processors-2407.211922025-01-30 https://scifaro.com/en/abs/edgellm-a-highly-efficient-cpu-fpga-heterogeneous-edge-accelerator-for-large-language-models-2407.213252025-03-03 https://scifaro.com/en/abs/blink-fast-automated-design-of-run-time-power-monitors-on-fpga-based-computing-platforms-2407.213672025-01-30 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https://scifaro.com/en/abs/toward-attention-based-tinyml-a-heterogeneous-accelerated-architecture-and-automated-deployment-flow-2408.024732025-01-10 https://scifaro.com/en/abs/finite-time-lyapunov-exponent-calculation-on-fpga-using-high-level-synthesis-tools-2408.027582024-08-07 https://scifaro.com/en/abs/evaluating-large-language-models-for-automatic-register-transfer-logic-generation-via-high-level-synthesis-2408.027932024-08-07 https://scifaro.com/en/abs/static-ir-drop-prediction-with-attention-u-net-and-saliency-based-explainability-2408.032922024-08-07 https://scifaro.com/en/abs/potential-and-limitation-of-high-frequency-cores-and-caches-2408.033082024-09-09 https://scifaro.com/en/abs/hetrax-energy-efficient-3d-heterogeneous-manycore-architecture-for-transformer-acceleration-2408.033972024-08-08 https://scifaro.com/en/abs/llm-aided-compilation-for-tensor-accelerators-2408.034082024-08-08 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https://scifaro.com/en/abs/efficient-edge-ai-deploying-convolutional-neural-networks-on-fpga-with-the-gemmini-accelerator-2408.074042024-08-15 https://scifaro.com/en/abs/development-of-simulation-model-for-single-carrier-transceiver-for-nanosatellite-2408.076552024-08-31 https://scifaro.com/en/abs/accelerating-mini-batch-hgnn-training-by-reducing-cuda-kernels-2408.084902024-08-19 https://scifaro.com/en/abs/r-hls-an-ir-for-dynamic-high-level-synthesis-and-memory-disambiguation-based-on-regions-and-state-edges-2408.087122024-08-19 https://scifaro.com/en/abs/xpikeformer-hybrid-analog-digital-hardware-acceleration-for-spiking-transformers-2408.087942025-04-23 https://scifaro.com/en/abs/h2pipe-high-throughput-cnn-inference-on-fpgas-with-high-bandwidth-memory-2408.092092024-08-20 https://scifaro.com/en/abs/in-memory-learning-automata-architecture-using-y-flash-cell-2408.094562024-08-20 https://scifaro.com/en/abs/cmd-a-cache-assisted-gpu-memory-deduplication-architecture-2408.094832024-08-20 https://scifaro.com/en/abs/tywaves-a-typed-waveform-viewer-for-chisel-2408.100822024-08-23 https://scifaro.com/en/abs/a-general-purpose-device-for-interaction-with-llms-2408.102302024-08-21 https://scifaro.com/en/abs/fpca-field-programmable-pixel-convolutional-array-for-extreme-edge-intelligence-2408.102332024-08-21 https://scifaro.com/en/abs/trim-triangular-input-movement-systolic-array-for-convolutional-neural-networks-architecture-and-hardware-implementation-2408.102432025-01-15 https://scifaro.com/en/abs/are-llms-any-good-for-high-level-synthesis-2408.104282024-08-21 https://scifaro.com/en/abs/system-level-design-space-exploration-for-high-level-synthesis-under-end-to-end-latency-constraints-2408.104312024-09-26 https://scifaro.com/en/abs/design-and-implementation-of-a-takum-arithmetic-hardware-codec-2408.105942025-11-27 https://scifaro.com/en/abs/hardware-implementation-of-projection-aggregation-decoders-for-reed-muller-codes-2408.108502024-08-21 https://scifaro.com/en/abs/revisiting-verilogeval-a-year-of-improvements-in-large-language-models-for-hardware-code-generation-2408.110532025-02-05 https://scifaro.com/en/abs/hima-hierarchical-quantum-microarchitecture-for-qubit-scaling-and-quantum-process-level-parallelism-2408.113112024-08-22 https://scifaro.com/en/abs/in-memory-computing-architecture-for-efficient-hardware-security-2408.115702024-08-22 https://scifaro.com/en/abs/anteumbler-non-invasive-antenna-orientation-error-measurement-for-wifi-aps-2408.116602024-08-22 https://scifaro.com/en/abs/floating-point-multiply-add-with-approximate-normalization-for-low-cost-matrix-engines-2408.119972024-08-23 https://scifaro.com/en/abs/virgo-cluster-level-matrix-unit-integration-in-gpus-for-scalability-and-energy-efficiency-2408.120732025-03-04 https://scifaro.com/en/abs/exposing-shadow-branches-2408.125922024-12-23 https://scifaro.com/en/abs/simopt-simulation-pass-for-speculative-optimisation-of-fpga-cad-flow-2408.126762024-08-26 https://scifaro.com/en/abs/an-architectural-error-metric-for-cnn-oriented-approximate-multipliers-2408.128362024-08-26 https://scifaro.com/en/abs/general-purpose-multicore-architectures-2408.129992025-01-28 https://scifaro.com/en/abs/nas-cap-deep-learning-driven-3-d-capacitance-extraction-with-neural-architecture-search-and-data-augmentation-2408.131952024-08-26 https://scifaro.com/en/abs/efficient-task-transfer-for-hls-dse-2408.132702024-08-27 https://scifaro.com/en/abs/site-cim-signed-ternary-computing-in-memory-for-ultra-low-precision-deep-neural-networks-2408.136172024-08-27 https://scifaro.com/en/abs/hapm-hardware-aware-pruning-method-for-cnn-hardware-accelerators-in-resource-constrained-devices-2408.140552024-08-27 https://scifaro.com/en/abs/synergistic-and-efficient-edge-host-communication-for-energy-harvesting-wireless-sensor-networks-2408.143792024-08-28 https://scifaro.com/en/abs/sparsity-aware-hardware-software-co-design-of-spiking-neural-networks-an-overview-2408.144372024-08-27 https://scifaro.com/en/abs/sihgnn-leveraging-properties-of-semantic-graphs-for-efficient-hgnn-acceleration-2408.150892024-08-28 https://scifaro.com/en/abs/corrigendum-to-a-systematic-study-of-ddr4-dram-faults-in-the-field-2408.153022024-08-29 https://scifaro.com/en/abs/shared-pim-enabling-concurrent-computation-and-data-flow-for-faster-processing-in-dram-2408.154892025-05-09 https://scifaro.com/en/abs/cgra4ml-a-hardware-software-framework-to-implement-neural-networks-for-scientific-edge-computing-2408.155612026-03-30 https://scifaro.com/en/abs/affordable-hpc-leveraging-small-clusters-for-big-data-and-graph-computing-2408.155682024-08-29 https://scifaro.com/en/abs/firefly-s-exploiting-dual-side-sparsity-for-spiking-neural-networks-acceleration-with-reconfigurable-spatial-architecture-2408.155782026-01-30 https://scifaro.com/en/abs/pc-indexed-data-address-translation-2408.158782026-04-02 https://scifaro.com/en/abs/accelerating-sensor-fusion-in-neuromorphic-computing-a-case-study-on-loihi-2-2408.160962024-08-30 https://scifaro.com/en/abs/pacim-a-sparsity-centric-hybrid-compute-in-memory-architecture-via-probabilistic-approximation-2408.162462024-09-02 https://scifaro.com/en/abs/timefloats-train-in-memory-with-time-domain-floating-point-scalar-products-2409.004952024-11-27 https://scifaro.com/en/abs/research-on-llm-acceleration-using-the-high-performance-risc-v-processor-xiangshan-nanhu-version-based-on-the-open-source-matrix-instruction-set-extension-vector-dot-product-2409.006612024-09-04 https://scifaro.com/en/abs/duplex-a-device-for-large-language-models-with-mixture-of-experts-grouped-query-attention-and-continuous-batching-2409.011412025-11-04 https://scifaro.com/en/abs/vlsi-hypergraph-partitioning-with-deep-learning-2409.013872024-09-04 https://scifaro.com/en/abs/reuse-and-blend-energy-efficient-optical-neural-network-enabled-by-weight-sharing-2409.018362024-09-10 https://scifaro.com/en/abs/global-optimizations-lightweight-dynamic-logic-for-concurrency-2409.022272024-09-05 https://scifaro.com/en/abs/register-aggregation-for-hardware-decompilation-2409.031192024-09-06 https://scifaro.com/en/abs/hardware-acceleration-of-llms-a-comprehensive-survey-and-comparison-2409.033842024-09-06 https://scifaro.com/en/abs/revealing-untapped-dsp-optimization-potentials-for-fpga-based-systolic-matrix-engines-2409.035082024-09-06 https://scifaro.com/en/abs/a-hardware-aware-gate-cutting-framework-for-practical-quantum-circuit-knitting-2409.038702024-09-09 https://scifaro.com/en/abs/an-analog-and-digital-hybrid-attention-accelerator-for-transformers-with-charge-based-in-memory-computing-2409.049402024-10-31 https://scifaro.com/en/abs/hydra-hybrid-data-multiplexing-and-run-time-layer-configurable-dnn-accelerator-2409.049762026-03-31 https://scifaro.com/en/abs/instinfer-in-storage-attention-offloading-for-cost-effective-long-context-llm-inference-2409.049922024-09-10 https://scifaro.com/en/abs/fast-generation-of-custom-floating-point-spatial-filters-on-fpgas-2409.058372024-09-10 https://scifaro.com/en/abs/rayflex-an-open-source-rtl-implementation-of-the-hardware-ray-tracer-datapath-2409.060002025-05-22 https://scifaro.com/en/abs/pim-mmu-a-memory-management-unit-for-accelerating-data-transfers-in-commercial-pim-systems-2409.062042024-09-11 https://scifaro.com/en/abs/maps-energy-reliability-tradeoff-management-in-autonomous-vehicles-through-llms-penetrated-science-2409.065582024-09-11 https://scifaro.com/en/abs/efficient-and-reliable-vector-similarity-search-using-asymmetric-encoding-with-nand-flash-for-many-class-few-shot-learning-2409.078322024-09-13 https://scifaro.com/en/abs/dynamic-simultaneous-multithreaded-architecture-2409.079032024-09-16 https://scifaro.com/en/abs/rethinking-programmed-i-o-for-fast-devices-cheap-cores-and-coherent-interconnects-2409.081412025-04-25 https://scifaro.com/en/abs/on-the-impact-of-isa-extension-on-energy-consumption-of-i-cache-in-extensible-processors-2409.082862024-09-16 https://scifaro.com/en/abs/analoggym-an-open-and-practical-testing-suite-for-analog-circuit-synthesis-2409.085342024-09-16 https://scifaro.com/en/abs/elasticai-creating-and-deploying-energy-efficient-deep-learning-accelerator-for-pervasive-computing-2409.090442024-09-17 https://scifaro.com/en/abs/cat-customized-transformer-accelerator-framework-on-versal-acap-2409.096892024-09-17 https://scifaro.com/en/abs/count2multiply-reliable-in-memory-high-radix-counting-2409.101362025-04-25 https://scifaro.com/en/abs/fsl-hdnn-a-5-7-tops-w-end-to-end-few-shot-learning-classifier-accelerator-with-feature-extraction-and-hyperdimensional-computing-2409.109182024-09-18 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https://scifaro.com/en/abs/a-high-throughput-hardware-accelerator-for-lempel-ziv-4-compression-algorithm-2409.124332024-09-20 https://scifaro.com/en/abs/accelerating-ai-and-computer-vision-for-satellite-pose-estimation-on-the-intel-myriad-x-embedded-soc-2409.129392024-09-20 https://scifaro.com/en/abs/craftrtl-high-quality-synthetic-data-generation-for-verilog-code-models-with-correct-by-construction-non-textual-representations-and-targeted-code-repair-2409.129932025-02-10 https://scifaro.com/en/abs/performance-and-power-systematic-evaluation-of-ai-workloads-on-accelerators-with-caraml-2409.129942025-03-14 https://scifaro.com/en/abs/towards-efficient-neuro-symbolic-ai-from-workload-characterization-to-hardware-architecture-2409.131532024-09-24 https://scifaro.com/en/abs/looptree-exploring-the-fused-layer-dataflow-accelerator-design-space-2409.136252024-10-15 https://scifaro.com/en/abs/protea-programmable-transformer-encoder-acceleration-on-fpga-2409.139752024-09-24 https://scifaro.com/en/abs/speed-a-scalable-risc-v-vector-processor-enabling-efficient-multi-precision-dnn-inference-2409.140172024-10-10 https://scifaro.com/en/abs/famous-flexible-accelerator-for-the-attention-mechanism-of-transformer-on-ultrascale-fpgas-2409.140232025-12-22 https://scifaro.com/en/abs/in-place-switch-reprogramming-based-slc-cache-design-for-hybrid-3d-ssds-2409.143602024-10-15 https://scifaro.com/en/abs/hardware-algorithm-co-design-for-real-time-i-o-control-with-improved-timing-accuracy-and-robustness-2409.147792024-09-24 https://scifaro.com/en/abs/mesc-re-thinking-algorithmic-priority-and-or-criticality-inversions-for-heterogeneous-mcss-2409.148372024-09-24 https://scifaro.com/en/abs/efficient-tabular-data-preprocessing-of-ml-pipelines-2409.149122024-09-24 https://scifaro.com/en/abs/exploring-and-exploiting-runtime-reconfigurable-floating-point-precision-in-scientific-computing-a-case-study-for-solving-pdes-2409.150732024-09-24 https://scifaro.com/en/abs/location-is-key-leveraging-large-language-model-for-functional-bug-localization-in-verilog-2409.151862024-10-01 https://scifaro.com/en/abs/laag-rv-llm-assisted-assertion-generation-for-rtl-design-verification-2409.152812024-09-25 https://scifaro.com/en/abs/cambricon-llm-a-chiplet-based-hybrid-architecture-for-on-device-inference-of-70b-llm-2409.156542024-09-25 https://scifaro.com/en/abs/design-of-a-reformed-array-logic-binary-multiplier-for-high-speed-computations-2409.164052024-09-26 https://scifaro.com/en/abs/pifs-rec-process-in-fabric-switch-for-large-scale-recommendation-system-inferences-2409.166332024-09-26 https://scifaro.com/en/abs/hurry-highly-utilized-reconfigurable-reram-based-in-situ-accelerator-with-multifunctionality-2409.166402024-09-26 https://scifaro.com/en/abs/the-interplay-of-computing-ethics-and-policy-in-brain-computer-interface-design-2409.174452024-09-27 https://scifaro.com/en/abs/towards-forever-access-for-implanted-brain-computer-interfaces-2409.174962024-09-27 https://scifaro.com/en/abs/swapping-centric-neural-recording-systems-2409.175412024-09-27 https://scifaro.com/en/abs/floonoc-a-645-gbps-link-0-15-pj-b-hop-open-source-noc-with-wide-physical-links-and-end-to-end-axi4-parallel-multi-stream-support-2409.176062025-03-28 https://scifaro.com/en/abs/vvteam-a-compact-behavioral-model-for-volatile-memristors-2409.177232025-07-22 https://scifaro.com/en/abs/voxel-cim-an-efficient-compute-in-memory-accelerator-for-voxel-based-point-cloud-neural-networks-2409.190772024-10-01 https://scifaro.com/en/abs/developing-cost-effective-drones-for-5g-non-terrestrial-network-research-and-experimentation-2409.193372024-10-01 https://scifaro.com/en/abs/fastflow-in-fpga-stacks-of-data-centers-2409.200992024-10-04 https://scifaro.com/en/abs/samips-a-synthesised-asynchronous-processor-2409.203882024-10-01 https://scifaro.com/en/abs/accelerating-pot-quantization-on-edge-devices-2409.204032024-10-23 https://scifaro.com/en/abs/neurovm-dynamic-neuromorphic-hardware-virtualization-2410.002952024-10-02 https://scifaro.com/en/abs/a-reconfigurable-approximate-computing-risc-v-platform-for-fault-tolerant-applications-2410.006222024-10-02 https://scifaro.com/en/abs/design-and-in-training-optimization-of-binary-search-adc-for-flexible-classifiers-2410.007372024-12-10 https://scifaro.com/en/abs/using-a-performance-model-to-implement-a-superscalar-cva6-2410.014422024-10-03 https://scifaro.com/en/abs/imagine-an-in-memory-accelerated-gemv-engine-overlay-2410.043672024-10-08 https://scifaro.com/en/abs/large-language-model-inference-acceleration-a-comprehensive-hardware-perspective-2410.044662025-06-16 https://scifaro.com/en/abs/hf-ntt-hazard-free-dataflow-accelerator-for-number-theoretic-transform-2410.048052024-10-08 https://scifaro.com/en/abs/secure-software-hardware-hybrid-in-field-testing-for-system-on-chip-2410.051092025-02-18 https://scifaro.com/en/abs/salient-store-enabling-smart-storage-for-continuous-learning-edge-servers-2410.054352024-10-10 https://scifaro.com/en/abs/openearable-exg-open-source-hardware-for-ear-based-biopotential-sensing-applications-2410.065332024-10-10 https://scifaro.com/en/abs/evaluation-of-run-time-energy-efficiency-using-controlled-approximation-in-a-risc-v-core-2410.070272024-10-10 https://scifaro.com/en/abs/a-survey-collaborative-hardware-and-software-design-in-the-era-of-large-language-models-2410.072652024-10-11 https://scifaro.com/en/abs/optimizing-high-level-synthesis-designs-with-retrieval-augmented-large-language-models-2410.073562024-10-11 https://scifaro.com/en/abs/optimized-spatial-architecture-mapping-flow-for-transformer-accelerators-2410.074072024-10-11 https://scifaro.com/en/abs/reducing-the-cost-of-dropout-in-flash-attention-by-hiding-rng-with-gemm-2410.075312025-07-08 https://scifaro.com/en/abs/the-bram-is-the-limit-shattering-myths-shaping-standards-and-building-scalable-pim-accelerators-2410.075462024-10-11 https://scifaro.com/en/abs/vclic-towards-fast-interrupt-handling-in-virtualized-risc-v-mixed-criticality-systems-2410.077982024-10-11 https://scifaro.com/en/abs/risc-v-v-vector-extension-rvv-with-reduced-number-of-vector-registers-2410.083962024-10-14 https://scifaro.com/en/abs/menage-mixed-signal-event-driven-neuromorphic-accelerator-for-edge-applications-2410.084032024-10-14 https://scifaro.com/en/abs/circuits-and-systems-for-embodied-ai-exploring-uj-multi-modal-perception-for-nano-uavs-on-the-kraken-shield-2410.090542024-10-15 https://scifaro.com/en/abs/gust-graph-edge-coloring-utilization-for-accelerating-sparse-matrix-vector-multiplication-2410.091062024-10-15 https://scifaro.com/en/abs/m-2-vit-accelerating-hybrid-vision-transformers-with-two-level-mixed-quantization-2410.091132024-10-15 https://scifaro.com/en/abs/energy-efficient-snn-architecture-using-3nm-finfet-multiport-sram-based-cim-with-online-learning-2410.091302024-10-15 https://scifaro.com/en/abs/mfit-multi-fidelity-thermal-modeling-for-2-5d-and-3d-multi-chiplet-architectures-2410.091882025-05-13 https://scifaro.com/en/abs/tackling-coherent-noise-in-quantum-computing-via-cross-layer-compiler-optimization-2410.096642024-10-15 https://scifaro.com/en/abs/messaging-based-adaptive-vector-computing-mavec-accelerator-for-ai-workloads-2410.099612026-02-05 https://scifaro.com/en/abs/work-in-progress-real-time-neural-network-inference-on-a-custom-risc-v-multicore-vector-processor-2410.103402024-10-15 https://scifaro.com/en/abs/dynamic-power-control-in-a-hardware-neural-network-with-error-configurable-mac-units-2410.105452024-10-15 https://scifaro.com/en/abs/voltage-controlled-magnetic-tunnel-junction-based-adc-less-global-shutter-processing-in-pixel-for-extreme-edge-intelligence-2410.105922024-10-15 https://scifaro.com/en/abs/theoretical-analysis-of-the-efficient-memory-matrix-storage-method-for-quantum-emulation-accelerators-with-gate-fusion-on-fpgas-2410.111462024-10-16 https://scifaro.com/en/abs/sorted-weight-sectioning-for-energy-efficient-unstructured-sparse-dnns-on-compute-in-memory-crossbars-2410.112982025-07-10 https://scifaro.com/en/abs/taming-performance-variability-caused-by-client-side-hardware-configuration-2410.115542024-10-16 https://scifaro.com/en/abs/dpd-neuralengine-a-22-nm-6-6-tops-w-mm-2-recurrent-neural-network-accelerator-for-wideband-power-amplifier-digital-pre-distortion-2410.117662025-07-03 https://scifaro.com/en/abs/mlperf-power-benchmarking-the-energy-efficiency-of-machine-learning-systems-from-microwatts-to-megawatts-for-sustainable-ai-2410.120322025-02-07 https://scifaro.com/en/abs/comet-towards-partical-w4a4kv4-llms-serving-2410.121682024-10-17 https://scifaro.com/en/abs/an-o-m-n-space-spatiotemporal-denoising-filter-with-cache-like-memories-for-dynamic-vision-sensors-2410.124232024-10-17 https://scifaro.com/en/abs/toleo-scaling-freshness-to-tera-scale-memory-using-cxl-and-pim-2410.127492024-10-17 https://scifaro.com/en/abs/rapidstream-ir-infrastructure-for-fpga-high-level-physical-synthesis-2410.130792024-10-18 https://scifaro.com/en/abs/trinity-a-general-purpose-fhe-accelerator-2410.134052024-10-18 https://scifaro.com/en/abs/shavette-low-power-neural-network-acceleration-via-algorithm-level-error-detection-and-undervolting-2410.134152025-05-12 https://scifaro.com/en/abs/per-bank-bandwidth-regulation-of-shared-last-level-cache-for-real-time-systems-2410.140032025-07-23 https://scifaro.com/en/abs/multi-diseases-detection-with-memristive-system-on-chip-2410.148822024-10-22 https://scifaro.com/en/abs/ianus-integrated-accelerator-based-on-npu-pim-unified-memory-system-2410.150082024-10-22 https://scifaro.com/en/abs/llc-intra-set-write-balancing-2410.153442024-10-22 https://scifaro.com/en/abs/automated-formal-verification-of-a-highly-configurable-register-generator-2410.154792024-10-22 https://scifaro.com/en/abs/design-of-a-64-bit-sqrt-csla-with-reduced-area-and-high-speed-applications-in-low-power-vlsi-circuits-2410.157362024-10-22 https://scifaro.com/en/abs/formalising-cxl-cache-coherence-2410.159082025-03-20 https://scifaro.com/en/abs/controlpulplet-a-flexible-real-time-multi-core-risc-v-controller-for-2-5d-systems-in-package-2410.159852025-08-14 https://scifaro.com/en/abs/saim-scalable-analog-ising-machine-for-solving-quadratic-binary-optimization-problems-2410.160792024-11-27 https://scifaro.com/en/abs/towards-efficient-imc-accelerator-design-through-joint-hardware-workload-co-optimization-2410.167592025-02-04 https://scifaro.com/en/abs/a-10-60-mu-w-150-gops-mixed-bit-width-sparse-cnn-accelerator-for-life-threatening-ventricular-arrhythmia-detection-2410.173952024-10-24 https://scifaro.com/en/abs/arcus-slo-management-for-accelerators-in-the-cloud-with-traffic-shaping-2410.175772024-10-24 https://scifaro.com/en/abs/fuzzwiz-fuzzing-framework-for-efficient-hardware-coverage-2410.177322025-12-11 https://scifaro.com/en/abs/pointer-an-energy-efficient-reram-based-point-cloud-recognition-accelerator-with-inter-layer-and-intra-layer-optimizations-2410.177822024-10-24 https://scifaro.com/en/abs/firepower-towards-a-foundation-with-generalizable-knowledge-for-architecture-level-power-modeling-2410.177892024-10-24 https://scifaro.com/en/abs/aras-an-adaptive-low-cost-reram-based-accelerator-for-dnns-2410.179312024-10-24 https://scifaro.com/en/abs/verifying-non-friendly-formal-verification-designs-can-we-start-earlier-2410.184542024-10-25 https://scifaro.com/en/abs/hpr-mul-an-area-and-energy-efficient-high-precision-redundancy-multiplier-by-approximate-computing-2410.201502024-10-29 https://scifaro.com/en/abs/architectural-solutions-for-high-speed-data-processing-demands-of-cern-lhc-detectors-with-fpga-and-high-level-synthesis-2410.204302024-10-29 https://scifaro.com/en/abs/spicepilot-navigating-spice-code-generation-and-simulation-with-ai-guidance-2410.205532024-10-29 https://scifaro.com/en/abs/efficient-reprogramming-of-memristive-crossbars-for-dnns-weight-sorting-and-bit-stucking-2410.217302025-07-10 https://scifaro.com/en/abs/a-host-ssd-collaborative-write-accelerator-for-lsm-tree-based-key-value-stores-2410.217602024-10-30 https://scifaro.com/en/abs/online-alignment-and-addition-in-multi-term-floating-point-adders-2410.219592024-10-30 https://scifaro.com/en/abs/pushing-the-performance-envelope-of-dnn-based-recommendation-systems-inference-on-gpus-2410.222492024-10-30 https://scifaro.com/en/abs/communication-characterization-of-ai-workloads-for-large-scale-multi-chiplet-accelerators-2410.222622025-02-13 https://scifaro.com/en/abs/systolic-array-data-flows-for-efficient-matrix-multiplication-in-deep-neural-networks-2410.225952024-10-31 https://scifaro.com/en/abs/an-event-based-digital-compute-in-memory-accelerator-with-flexible-operand-resolution-and-layer-wise-weight-output-stationarity-2410.230822024-10-31 https://scifaro.com/en/abs/educating-for-hardware-specialization-in-the-chiplet-era-a-path-for-the-hpc-community-2410.231272024-10-31 https://scifaro.com/en/abs/fveval-understanding-language-model-capabilities-in-formal-verification-of-digital-hardware-2410.232992024-11-01 https://scifaro.com/en/abs/upanns-enhancing-billion-scale-anns-efficiency-with-real-world-pim-architecture-2410.238052025-08-21 https://scifaro.com/en/abs/deepseq2-enhanced-sequential-circuit-learning-with-disentangled-representations-2411.005302024-11-04 https://scifaro.com/en/abs/multilayer-dataflow-orchestrate-butterfly-sparsity-to-accelerate-attention-computation-2411.007342024-11-26 https://scifaro.com/en/abs/bf-imna-a-bit-fluid-in-memory-neural-architecture-for-neural-network-acceleration-2411.014172024-11-05 https://scifaro.com/en/abs/energy-aware-fpga-implementation-of-spiking-neural-network-with-lif-neurons-2411.016282024-11-05 https://scifaro.com/en/abs/spidr-a-reconfigurable-digital-compute-in-memory-spiking-neural-network-accelerator-for-event-based-perception-2411.028542024-11-06 https://scifaro.com/en/abs/hardware-for-converting-floating-point-to-the-microscaling-mx-format-2411.031492024-11-06 https://scifaro.com/en/abs/dp-hls-a-high-level-synthesis-framework-for-accelerating-dynamic-programming-algorithms-in-bioinformatics-2411.033982024-11-07 https://scifaro.com/en/abs/metrex-a-benchmark-for-verilog-code-metric-reasoning-using-llms-2411.034712025-01-28 https://scifaro.com/en/abs/tataa-programmable-mixed-precision-transformer-acceleration-with-a-transformable-arithmetic-architecture-2411.036972024-11-07 https://scifaro.com/en/abs/accelerating-dna-read-mapping-with-digital-processing-in-memory-2411.038322024-11-22 https://scifaro.com/en/abs/efficient-message-passing-architecture-for-gcn-training-on-hbm-based-fpgas-with-orthogonal-topology-on-chip-networks-2411.038572024-11-07 https://scifaro.com/en/abs/the-survey-of-chiplet-based-integrated-architecture-an-eda-perspective-2411.044102024-11-08 https://scifaro.com/en/abs/further-evaluations-of-a-didactic-cpu-visual-simulator-cpuvsim-2411.052292024-11-11 https://scifaro.com/en/abs/microscopiq-accelerating-foundational-models-through-outlier-aware-microscaling-quantization-2411.052822025-05-01 https://scifaro.com/en/abs/ancoef-asynchronous-neuromorphic-algorithm-hardware-co-exploration-framework-with-a-fully-asynchronous-simulator-2411.060592024-11-12 https://scifaro.com/en/abs/a-review-of-sram-based-compute-in-memory-circuits-2411.060792024-11-25 https://scifaro.com/en/abs/optima-design-space-exploration-of-discharge-based-in-sram-computing-quantifying-energy-accuracy-trade-offs-2411.068462024-11-12 https://scifaro.com/en/abs/16-years-of-spec-power-an-analysis-of-x86-energy-efficiency-trends-2411.070622024-11-12 https://scifaro.com/en/abs/rpcacc-a-high-performance-and-reconfigurable-pcie-attached-rpc-accelerator-2411.076322024-11-19 https://scifaro.com/en/abs/web-based-simulator-of-superscalar-risc-v-processors-2411.077212024-11-13 https://scifaro.com/en/abs/mantis-a-mixed-signal-near-sensor-convolutional-imager-soc-using-charge-domain-4b-weighted-5-to-84-tops-w-mac-operations-for-feature-extraction-and-region-of-interest-detection-2411.079462024-11-13 https://scifaro.com/en/abs/a-novel-extensible-simulation-framework-for-cxl-enabled-systems-2411.083122024-11-14 https://scifaro.com/en/abs/everything-you-wanted-to-know-about-consumer-light-management-in-smart-energy-2411.083532024-11-14 https://scifaro.com/en/abs/a-system-level-performance-evaluation-for-superconducting-digital-systems-2411.086452024-11-14 https://scifaro.com/en/abs/reducing-adc-front-end-costs-during-training-of-on-sensor-printed-multilayer-perceptrons-2411.086742024-12-10 https://scifaro.com/en/abs/pimcomp-an-end-to-end-dnn-compiler-for-processing-in-memory-accelerators-2411.091592024-11-15 https://scifaro.com/en/abs/noncontact-multi-point-vital-sign-monitoring-with-mmwave-mimo-radar-2411.092012024-11-15 https://scifaro.com/en/abs/sustainable-hardware-specialization-2411.093152024-11-15 https://scifaro.com/en/abs/opengemm-a-high-utilization-gemm-accelerator-generator-with-lightweight-risc-v-control-and-tight-memory-coupling-2411.095432024-11-22 https://scifaro.com/en/abs/architectural-exploration-of-application-specific-resonant-sram-compute-in-memory-rcim-2411.095462024-11-15 https://scifaro.com/en/abs/specpcm-a-low-power-pcm-based-in-memory-computing-accelerator-for-full-stack-mass-spectrometry-analysis-2411.097602024-11-18 https://scifaro.com/en/abs/systolic-arrays-and-structured-pruning-co-design-for-efficient-transformers-in-edge-systems-2411.102852025-05-13 https://scifaro.com/en/abs/appsign-multi-level-approximate-computing-for-real-time-traffic-sign-recognition-in-autonomous-vehicles-2411.109882024-11-19 https://scifaro.com/en/abs/timing-driven-approximate-logic-synthesis-based-on-double-chase-grey-wolf-optimizer-2411.109902024-11-19 https://scifaro.com/en/abs/asim-modeling-and-analyzing-inference-accuracy-of-sram-based-analog-cim-circuits-2411.110222025-09-03 https://scifaro.com/en/abs/silvia-automated-superword-level-parallelism-exploitation-via-hls-specific-llvm-passes-for-compute-intensive-fpga-accelerators-2411.113842024-11-21 https://scifaro.com/en/abs/an-efficient-multicast-addressing-encoding-scheme-for-multi-core-neuromorphic-processors-2411.115452024-11-19 https://scifaro.com/en/abs/lutmul-exceed-conventional-fpga-roofline-limit-by-lut-based-efficient-multiplication-for-neural-network-inference-2411.118522024-11-20 https://scifaro.com/en/abs/automatically-improving-llm-based-verilog-generation-using-eda-tool-feedback-2411.118562025-03-06 https://scifaro.com/en/abs/forward-and-reverse-converters-for-the-moduli-set-2-2q-1-2-q-2-q-1-pm1-2411.122132024-11-20 https://scifaro.com/en/abs/advancing-cloud-computing-capabilities-on-gem5-by-implementing-the-risc-v-hypervisor-extension-2411.124442024-11-21 https://scifaro.com/en/abs/travel-time-based-task-mapping-for-noc-based-dnn-accelerator-2411.127102025-09-03 https://scifaro.com/en/abs/veryl-a-new-hardware-description-language-as-an-altarnative-to-systemverilog-2411.129832024-11-21 https://scifaro.com/en/abs/topkima-former-low-energy-low-latency-inference-for-transformers-using-top-k-in-memory-adc-2411.130502024-11-21 https://scifaro.com/en/abs/generalized-ping-pong-off-chip-memory-bandwidth-centric-pipelining-strategy-for-processing-in-memory-accelerators-2411.130542024-11-21 https://scifaro.com/en/abs/hardware-accelerators-for-artificial-intelligence-2411.137172024-12-19 https://scifaro.com/en/abs/dissecting-conditional-branch-predictors-of-apple-firestorm-and-qualcomm-oryon-for-software-optimization-and-architectural-analysis-2411.139002024-11-22 https://scifaro.com/en/abs/cktso-high-performance-parallel-sparse-linear-solver-for-general-circuit-simulations-2411.140822024-11-28 https://scifaro.com/en/abs/masala-chai-a-large-scale-spice-netlist-dataset-for-analog-circuits-by-harnessing-ai-2411.142992025-03-25 https://scifaro.com/en/abs/assertllm-generating-hardware-verification-assertions-from-design-specifications-via-multi-llms-2411.144362024-11-25 https://scifaro.com/en/abs/swift-a-multi-fpga-framework-for-scaling-up-accelerated-graph-analytics-2411.145542024-11-25 https://scifaro.com/en/abs/scalable-wavelength-arbitration-for-microring-based-dwdm-transceivers-2411.148102025-03-27 https://scifaro.com/en/abs/teaching-experiences-using-the-rvfpga-package-2411.149542026-02-10 https://scifaro.com/en/abs/exploring-the-sparsity-quantization-interplay-on-a-novel-hybrid-snn-event-driven-architecture-2411.154092024-11-26 https://scifaro.com/en/abs/automatic-high-quality-verilog-assertion-generation-through-subtask-focused-fine-tuned-llms-and-iterative-prompting-2411.154422024-11-26 https://scifaro.com/en/abs/an-affordable-experimental-technique-for-sram-write-margin-characterization-for-nanometer-cmos-technologies-2411.155212024-11-26 https://scifaro.com/en/abs/a-prototype-based-framework-to-design-scalable-heterogeneous-socs-with-fine-grained-dfs-2411.155742025-01-07 https://scifaro.com/en/abs/anda-unlocking-efficient-llm-inference-with-a-variable-length-grouped-activation-data-format-2411.159822025-05-13 https://scifaro.com/en/abs/performance-implications-of-multi-chiplet-neural-processing-units-on-autonomous-driving-perception-2411.160072024-11-26 https://scifaro.com/en/abs/uvllm-an-automated-universal-rtl-verification-framework-using-llms-2411.162382024-11-26 https://scifaro.com/en/abs/syndcim-a-performance-aware-digital-computing-in-memory-compiler-with-multi-spec-oriented-subcircuit-synthesis-2411.168062025-01-07 https://scifaro.com/en/abs/pim-ai-a-novel-architecture-for-high-efficiency-llm-inference-2411.173092024-12-02 https://scifaro.com/en/abs/efficient-transformer-adaptation-for-analog-in-memory-computing-via-low-rank-adapters-2411.173672026-03-24 https://scifaro.com/en/abs/softmap-software-hardware-co-design-for-integer-only-softmax-on-associative-processors-2411.178472024-11-28 https://scifaro.com/en/abs/calibrating-drampower-model-for-hpc-a-runtime-perspective-from-real-time-measurements-2411.179602025-09-04 https://scifaro.com/en/abs/reconfigurable-stream-network-architecture-2411.179662025-06-17 https://scifaro.com/en/abs/flexibit-fully-flexible-precision-bit-parallel-accelerator-architecture-for-arbitrary-mixed-precision-ai-2411.180652025-06-05 https://scifaro.com/en/abs/high-level-surface-code-decoding-via-parallel-ffnns-on-cim-platforms-2411.180902025-07-08 https://scifaro.com/en/abs/a-65-nm-reliable-6t-cmos-sram-cell-with-minimum-size-transistors-2411.181142024-11-28 https://scifaro.com/en/abs/a-runtime-adaptive-transformer-neural-network-accelerator-on-fpgas-2411.181482025-12-30 https://scifaro.com/en/abs/efficient-nonlinear-function-approximation-in-analog-resistive-crossbars-for-recurrent-neural-networks-2411.182712024-11-28 https://scifaro.com/en/abs/cxl-interference-analysis-and-characterization-in-modern-computer-systems-2411.183082024-11-28 https://scifaro.com/en/abs/quadol-a-quality-driven-approximate-logic-synthesis-method-exploiting-dual-output-luts-for-modern-fpgas-2411.183302025-09-10 https://scifaro.com/en/abs/stoch-imc-a-bit-parallel-stochastic-in-memory-computing-architecture-based-on-stt-mram-2411.193442024-12-03 https://scifaro.com/en/abs/core-placement-optimization-of-many-core-brain-inspired-near-storage-systems-for-spiking-neural-network-training-2411.194302025-05-21 https://scifaro.com/en/abs/c2hlsc-leveraging-large-language-models-to-bridge-the-software-to-hardware-design-gap-2412.002142025-05-20 https://scifaro.com/en/abs/instruction-scheduling-in-the-saturn-vector-unit-2412.009972024-12-03 https://scifaro.com/en/abs/fast-bipartitioned-hybrid-adder-utilizing-carry-select-and-carry-lookahead-logic-2412.017642024-12-03 https://scifaro.com/en/abs/compromising-the-intelligence-of-modern-dnns-on-the-effectiveness-of-targeted-rowpress-2412.021562024-12-04 https://scifaro.com/en/abs/ml-based-aig-timing-prediction-to-enhance-logic-optimization-2412.022682024-12-04 https://scifaro.com/en/abs/prefixllm-llm-aided-prefix-circuit-design-2412.025942024-12-04 https://scifaro.com/en/abs/binsparx-sparsified-binary-neural-networks-for-reduced-hardware-non-idealities-in-xbar-arrays-2412.035532024-12-05 https://scifaro.com/en/abs/distributed-inference-with-minimal-off-chip-traffic-for-transformers-on-low-power-mcus-2412.043722025-03-27 https://scifaro.com/en/abs/eda-aware-rtl-generation-with-large-language-models-2412.044852024-12-09 https://scifaro.com/en/abs/towards-performance-aware-allocation-for-accelerated-machine-learning-on-gpu-ssd-systems-2412.045692024-12-10 https://scifaro.com/en/abs/gaze-into-the-pattern-characterizing-spatial-patterns-with-internal-temporal-correlations-for-hardware-prefetching-2412.052112024-12-09 https://scifaro.com/en/abs/risc-v-word-size-modular-instructions-for-residue-number-systems-2412.052862024-12-10 https://scifaro.com/en/abs/memristor-based-selective-convolutional-circuit-for-high-density-salt-and-pepper-noise-removal-2412.052902024-12-10 https://scifaro.com/en/abs/doceda-automated-extraction-and-design-of-analog-circuits-from-documents-with-large-language-model-2412.053012024-12-10 https://scifaro.com/en/abs/a-high-energy-efficiency-multi-core-neuromorphic-architecture-for-deep-snn-training-2412.053022024-12-31 https://scifaro.com/en/abs/drc-coder-automated-drc-checker-code-generation-using-llm-autonomous-agent-2412.053112024-12-10 https://scifaro.com/en/abs/the-tiny-median-filter-a-small-size-flexible-arbitrary-percentile-finder-scheme-suitable-for-fpga-implementation-2412.053202024-12-10 https://scifaro.com/en/abs/impact-inmemory-computing-architecture-based-on-y-flash-technology-for-coalesced-tsetlin-machine-inference-2412.053272024-12-10 https://scifaro.com/en/abs/branch-target-buffer-reverse-engineering-on-arm-2412.054132024-12-10 https://scifaro.com/en/abs/asc-hook-fast-and-transparent-system-call-hook-for-arm-2412.057842025-06-24 https://scifaro.com/en/abs/signal-prediction-for-digital-circuits-by-sigmoidal-approximations-using-neural-networks-2412.058772024-12-10 https://scifaro.com/en/abs/a-flexible-template-for-edge-generative-ai-with-high-accuracy-accelerated-softmax-gelu-2412.063212024-12-10 https://scifaro.com/en/abs/sequential-printed-mlp-circuits-for-super-tinyml-multi-sensory-applications-2412.065422024-12-10 https://scifaro.com/en/abs/pyranet-a-multi-layered-hierarchical-dataset-for-verilog-2412.069472025-09-22 https://scifaro.com/en/abs/mage-a-multi-agent-engine-for-automated-rtl-code-generation-2412.078222024-12-12 https://scifaro.com/en/abs/enhancing-cgra-efficiency-through-aligned-compute-and-communication-provisioning-2412.081372024-12-13 https://scifaro.com/en/abs/empirical-measurements-of-ai-training-power-demand-on-a-gpu-accelerated-node-2412.086022025-03-25 https://scifaro.com/en/abs/dip-a-scalable-energy-efficient-systolic-array-for-matrix-multiplication-acceleration-2412.097092025-08-07 https://scifaro.com/en/abs/aieda-agentic-ai-design-framework-for-digital-asic-system-design-2412.097452024-12-16 https://scifaro.com/en/abs/panacea-novel-dnn-accelerator-using-accuracy-preserving-asymmetric-quantization-and-energy-saving-bit-slice-sparsity-2412.100592024-12-16 https://scifaro.com/en/abs/neuro-photonix-enabling-near-sensor-neuro-symbolic-ai-computing-on-silicon-photonics-substrate-2412.101872024-12-16 https://scifaro.com/en/abs/integrating-hw-sw-functionality-for-flexible-wireless-radio-2412.105902024-12-17 https://scifaro.com/en/abs/flex-pe-flexible-and-simd-multi-precision-processing-element-for-ai-workloads-2412.117022026-02-12 https://scifaro.com/en/abs/towards-understanding-systems-trade-offs-in-retrieval-augmented-generation-model-inference-2412.118542024-12-17 https://scifaro.com/en/abs/fingrav-methodology-for-fine-grain-gpu-power-visibility-and-insights-2412.124262025-04-01 https://scifaro.com/en/abs/design-and-performance-analysis-of-an-ultra-low-power-integrate-and-fire-neuron-circuit-using-nanoscale-side-contacted-field-effect-diode-technology-2412.124432024-12-18 https://scifaro.com/en/abs/if-zkp-intel-fpga-based-acceleration-of-zero-knowledge-proofs-2412.124812024-12-18 https://scifaro.com/en/abs/optimizing-ml-concurrent-computation-and-communication-with-gpu-dma-engines-2412.143352025-04-28 https://scifaro.com/en/abs/relaxed-exception-semantics-for-arm-a-extended-version-2412.151402024-12-20 https://scifaro.com/en/abs/polaris-multi-fidelity-design-space-exploration-of-deep-learning-accelerators-2412.155482024-12-23 https://scifaro.com/en/abs/a-survey-on-fpga-based-accelerator-for-ml-models-2412.156662024-12-23 https://scifaro.com/en/abs/switching-frequency-as-fpga-monitor-studying-degradation-and-ageing-prognosis-at-large-scale-2412.157202024-12-23 https://scifaro.com/en/abs/dfmodel-design-space-optimization-of-large-scale-systems-exploiting-dataflow-mappings-2412.164322024-12-24 https://scifaro.com/en/abs/leveraging-highly-approximated-multipliers-in-dnn-inference-2412.167572024-12-24 https://scifaro.com/en/abs/agile-tlb-prefetching-and-prediction-replacement-policy-2412.172032026-03-23 https://scifaro.com/en/abs/tubgemm-energy-efficient-and-sparsity-effective-temporal-unary-binary-based-matrix-multiply-unit-2412.179552024-12-25 https://scifaro.com/en/abs/tugemm-area-power-efficient-temporal-unary-gemm-architecture-for-low-precision-edge-ai-2412.179662024-12-25 https://scifaro.com/en/abs/tnngen-automated-design-of-neuromorphic-sensory-processing-units-for-time-series-clustering-2412.179772024-12-25 https://scifaro.com/en/abs/gcn-abft-low-cost-online-error-checking-for-graph-convolutional-networks-2412.185342024-12-25 https://scifaro.com/en/abs/reducedlut-table-decomposition-with-don-t-care-conditions-2412.185792025-01-03 https://scifaro.com/en/abs/a-power-efficient-hardware-implementation-of-l-mul-2412.189482024-12-30 https://scifaro.com/en/abs/tempus-core-area-power-efficient-temporal-unary-convolution-core-for-low-precision-edge-dlas-2412.190022024-12-30 https://scifaro.com/en/abs/evolution-challenges-and-optimization-in-computer-architecture-the-role-of-reconfigurable-systems-2412.192342024-12-30 https://scifaro.com/en/abs/memory-centric-computing-recent-advances-in-processing-in-dram-2412.192752024-12-30 https://scifaro.com/en/abs/atim-autotuning-tensor-programs-for-processing-in-dram-2412.196302025-06-03 https://scifaro.com/en/abs/imagine-an-8-to-1b-22nm-fd-soi-compute-in-memory-cnn-accelerator-with-an-end-to-end-analog-charge-based-0-15-8pops-w-macro-featuring-distribution-aware-data-reshaping-2412.197502024-12-30 https://scifaro.com/en/abs/chipalign-instruction-alignment-in-large-language-models-for-chip-design-via-geodesic-interpolation-2412.198192025-07-17 https://scifaro.com/en/abs/nanoscaling-floating-point-nxfp-nanomantissa-adaptive-microexponents-and-code-recycling-for-direct-cast-compression-of-large-language-models-2412.198212024-12-31 https://scifaro.com/en/abs/analogxpert-automating-analog-topology-synthesis-by-incorporating-circuit-design-expertise-into-large-language-models-2412.198242025-06-17 https://scifaro.com/en/abs/gformer-accelerating-large-language-models-with-optimized-transformers-on-gaudi-processors-2412.198292024-12-31 https://scifaro.com/en/abs/a-fully-hardware-implemented-accelerator-design-in-reram-analog-computing-without-adcs-2412.198692024-12-31 https://scifaro.com/en/abs/non-interfering-on-line-and-in-field-soc-testing-2412.199242024-12-31 https://scifaro.com/en/abs/pimphony-overcoming-bandwidth-and-capacity-inefficiency-in-pim-based-long-context-llm-inference-system-2412.201662025-12-29 https://scifaro.com/en/abs/integer-representations-in-ieee-754-posit-and-takum-arithmetics-2412.202732025-12-01 https://scifaro.com/en/abs/greenllm-disaggregating-large-language-model-serving-on-heterogeneous-gpus-for-lower-carbon-emissions-2412.203222024-12-31 https://scifaro.com/en/abs/wavelet-based-frequency-detection-using-fpgas-2412.203512024-12-31 https://scifaro.com/en/abs/open-source-heterogeneous-socs-for-ai-the-pulp-platform-experience-2412.203912024-12-31 https://scifaro.com/en/abs/a-novel-fpga-based-cnn-hardware-accelerator-optimization-for-convolutional-layers-using-karatsuba-ofman-multiplier-2412.203932024-12-31 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https://scifaro.com/en/abs/ic-d2s-a-hybrid-ising-classical-machines-data-driven-qubo-solver-method-2502.139472025-02-20 https://scifaro.com/en/abs/ndpage-efficient-address-translation-for-near-data-processing-architectures-via-tailored-page-table-2502.142202025-02-21 https://scifaro.com/en/abs/micro-blossom-accelerated-minimum-weight-perfect-matching-decoding-for-quantum-error-correction-2502.147872025-02-21 https://scifaro.com/en/abs/papi-exploiting-dynamic-parallelism-in-large-language-model-decoding-with-a-processing-in-memory-enabled-computing-system-2502.154702025-02-28 https://scifaro.com/en/abs/jexplore-design-space-exploration-tool-for-nvidia-jetson-boards-2502.157732025-02-26 https://scifaro.com/en/abs/deeprtl-bridging-verilog-understanding-and-generation-with-a-unified-representation-model-2502.158322025-02-27 https://scifaro.com/en/abs/an-smt-formalization-of-mixed-precision-matrix-multiplication-modeling-three-generations-of-tensor-cores-2502.159992025-02-25 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https://scifaro.com/en/abs/review-of-machine-learning-for-micro-electronic-design-verification-2503.116872025-03-18 https://scifaro.com/en/abs/a-comparison-of-the-cerebras-wafer-scale-integration-technology-with-nvidia-gpu-based-systems-for-artificial-intelligence-2503.116982025-03-18 https://scifaro.com/en/abs/edea-efficient-dual-engine-accelerator-for-depthwise-separable-convolution-with-direct-data-transfer-2503.117072025-03-18 https://scifaro.com/en/abs/a-systematic-approach-for-multi-objective-double-side-clock-tree-synthesis-2503.125122025-05-12 https://scifaro.com/en/abs/sparselut-sparse-connectivity-optimization-for-lookup-table-based-deep-neural-networks-2503.128292025-03-18 https://scifaro.com/en/abs/open3dbench-open-source-benchmark-for-3d-ic-backend-implementation-and-ppa-evaluation-2503.129462026-04-07 https://scifaro.com/en/abs/roma-a-read-only-memory-based-accelerator-for-qlora-based-on-device-llm-2503.129882026-03-03 https://scifaro.com/en/abs/hermes-high-performance-risc-v-memory-hierarchy-for-ml-workloads-2503.130642025-03-25 https://scifaro.com/en/abs/managing-hybrid-solid-state-drives-using-large-language-models-2503.131052025-03-18 https://scifaro.com/en/abs/limca-llm-for-automating-analog-in-memory-computing-architecture-design-exploration-2503.133012025-03-18 https://scifaro.com/en/abs/vericontaminated-assessing-llm-driven-verilog-coding-for-data-contamination-2503.135722025-06-13 https://scifaro.com/en/abs/flexstep-enabling-flexible-error-detection-in-multi-many-core-real-time-systems-2503.138482025-03-19 https://scifaro.com/en/abs/streamlining-simd-isa-extensions-with-takum-arithmetic-a-case-study-on-intel-avx10-2-2503.140672025-11-27 https://scifaro.com/en/abs/retrospective-a-cordic-based-configurable-activation-function-for-nn-applications-2503.143542026-02-13 https://scifaro.com/en/abs/nectar-a-heterogeneous-risc-v-soc-for-language-model-inference-in-intel-16-2503.147082025-03-20 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https://scifaro.com/en/abs/turtle-a-unified-evaluation-of-llms-for-rtl-generation-2504.019862025-06-02 https://scifaro.com/en/abs/pim-llm-a-high-throughput-hybrid-pim-architecture-for-1-bit-llms-2504.019942025-04-04 https://scifaro.com/en/abs/arcane-adaptive-risc-v-cache-architecture-for-near-memory-extensions-2504.025332025-04-09 https://scifaro.com/en/abs/unlocking-the-amd-neural-processing-unit-for-ml-training-on-the-client-using-bare-metal-programming-tools-2504.030832025-04-07 https://scifaro.com/en/abs/ndft-accelerating-density-functional-theory-calculations-via-hardware-software-co-design-on-near-data-computing-system-2504.034512025-04-07 https://scifaro.com/en/abs/mempool-flavors-between-versatility-and-specialization-in-a-risc-v-manycore-cluster-2504.036752025-04-08 https://scifaro.com/en/abs/fused-tiled-layers-minimizing-data-movement-on-risc-v-socs-with-software-managed-caches-2504.036762025-04-08 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https://scifaro.com/en/abs/learning-cache-coherence-traffic-for-noc-routing-design-2504.040052025-06-04 https://scifaro.com/en/abs/multi-phase-coupled-cmos-ring-oscillator-based-potts-machine-2504.042232025-04-08 https://scifaro.com/en/abs/virtual-memory-for-real-time-systems-using-hpmp-2504.044982025-04-08 https://scifaro.com/en/abs/n-torc-native-tensor-optimizer-for-real-time-constraints-2504.046612025-04-08 https://scifaro.com/en/abs/feriver-an-fpga-assisted-emulated-framework-for-rtl-verification-of-risc-v-processors-2504.052842025-04-08 https://scifaro.com/en/abs/boole-exact-symbolic-reasoning-via-boolean-equality-saturation-2504.055772025-04-22 https://scifaro.com/en/abs/cva6-vmrt-a-modular-approach-towards-time-predictable-virtual-memory-in-a-64-bit-application-class-risc-v-processor-2504.057182025-04-09 https://scifaro.com/en/abs/spikestream-accelerating-spiking-neural-network-inference-on-risc-v-clusters-with-sparse-computation-extensions-2504.061342025-04-09 https://scifaro.com/en/abs/need-for-zkspeed-accelerating-hyperplonk-for-zero-knowledge-proofs-2504.062112025-08-07 https://scifaro.com/en/abs/bottom-up-generation-of-verilog-designs-for-testing-eda-tools-2504.062952025-04-10 https://scifaro.com/en/abs/membrane-accelerating-database-analytics-with-bank-level-dram-pim-filtering-2504.064732025-04-10 https://scifaro.com/en/abs/fetta-flexible-and-efficient-hardware-accelerator-for-tensorized-neural-network-training-2504.064742026-03-31 https://scifaro.com/en/abs/beyond-moore-s-law-harnessing-the-redshift-of-generative-ai-with-effective-hardware-software-co-design-2504.065312025-04-10 https://scifaro.com/en/abs/introducing-the-arm-membench-throughput-benchmark-2504.068132025-04-10 https://scifaro.com/en/abs/neural-signal-compression-using-raman-tinyml-accelerator-for-bci-applications-2504.069962025-09-03 https://scifaro.com/en/abs/cimba-accelerating-genome-sequencing-through-on-device-basecalling-via-compute-in-memory-2504.072982025-04-11 https://scifaro.com/en/abs/unicaim-a-unified-cam-cim-architecture-with-static-dynamic-kv-cache-pruning-for-efficient-long-context-llm-inference-2504.074792025-04-11 https://scifaro.com/en/abs/a-950-mhz-simt-soft-processor-2504.075382025-04-11 https://scifaro.com/en/abs/just-testit-an-sbst-approach-to-automate-system-integration-testing-2504.075552025-04-11 https://scifaro.com/en/abs/quadrilatero-a-risc-v-programmable-matrix-coprocessor-for-low-power-edge-applications-2504.075652025-04-11 https://scifaro.com/en/abs/high-level-synthesis-of-digital-circuits-from-template-haskell-and-sdf-ap-2504.075852025-04-11 https://scifaro.com/en/abs/high-level-synthesis-using-sdf-ap-template-haskell-quasiquotes-and-gadts-to-generate-circuits-from-hierarchical-input-specification-2504.075952025-04-11 https://scifaro.com/en/abs/empowering-vector-architectures-for-ml-the-camp-architecture-for-matrix-multiplication-2504.081372025-04-14 https://scifaro.com/en/abs/efficient-architecture-for-risc-v-vector-memory-access-2504.083342025-04-17 https://scifaro.com/en/abs/mixdit-accelerating-image-diffusion-transformer-inference-with-mixed-precision-mx-quantization-2504.083982025-04-14 https://scifaro.com/en/abs/an-fpga-compiler-for-on-the-fly-adaptive-cnn-deployment-and-reconfiguration-2504.085342025-06-12 https://scifaro.com/en/abs/mgs-markov-greedy-sums-for-accurate-low-bitwidth-floating-point-accumulation-2504.090722025-04-15 https://scifaro.com/en/abs/a-case-for-kolmogorov-arnold-networks-in-prefetching-towards-low-latency-generalizable-ml-based-prefetchers-2504.090742025-04-15 https://scifaro.com/en/abs/leveraging-application-specific-knowledge-for-energy-efficient-deep-learning-accelerators-on-resource-constrained-fpgas-2504.091512025-04-15 https://scifaro.com/en/abs/nettag-a-multimodal-rtl-and-layout-aligned-netlist-foundation-model-via-text-attributed-graph-2504.092602025-04-15 https://scifaro.com/en/abs/looplynx-a-scalable-dataflow-architecture-for-efficient-llm-inference-2504.095612025-04-15 https://scifaro.com/en/abs/gama-high-performance-gemm-acceleration-on-amd-versal-ml-optimized-ai-engines-2504.096882025-09-01 https://scifaro.com/en/abs/mist-a-co-design-framework-for-heterogeneous-multi-stage-llm-inference-2504.097752026-04-22 https://scifaro.com/en/abs/carbon-efficient-3d-dnn-acceleration-optimizing-performance-and-sustainability-2504.098512025-05-30 https://scifaro.com/en/abs/ember-a-compiler-for-efficient-embedding-operations-on-decoupled-access-execute-architectures-2504.098702025-04-15 https://scifaro.com/en/abs/graph-neural-networks-based-analog-circuit-link-prediction-2504.102402025-11-19 https://scifaro.com/en/abs/araos-analyzing-the-impact-of-virtual-memory-management-on-vector-unit-performance-2504.103452025-04-15 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https://scifaro.com/en/abs/online-training-and-inference-system-on-edge-fpga-using-delayed-feedback-reservoir-2504.119702025-04-17 https://scifaro.com/en/abs/subitizing-inspired-large-language-models-for-floorplanning-2504.120762025-04-17 https://scifaro.com/en/abs/hls-eval-a-benchmark-and-framework-for-evaluating-llms-on-high-level-synthesis-design-tasks-2504.122682025-10-27 https://scifaro.com/en/abs/fast-parameter-optimization-of-delayed-feedback-reservoir-with-backpropagation-and-gradient-descent-2504.123632025-04-18 https://scifaro.com/en/abs/mixed-structural-choice-operator-enhancing-technology-mapping-with-heterogeneous-representations-2504.128242025-04-18 https://scifaro.com/en/abs/metadse-a-few-shot-meta-learning-framework-for-cross-workload-cpu-design-space-exploration-2504.135682025-04-21 https://scifaro.com/en/abs/a-cmos-probabilistic-computing-chip-with-in-situ-hardware-aware-learning-2504.140702025-05-01 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https://scifaro.com/en/abs/forgebench-a-machine-learning-benchmark-suite-and-auto-generation-framework-for-next-generation-hls-tools-2504.151852025-04-22 https://scifaro.com/en/abs/vericoder-enhancing-llm-based-rtl-code-generation-through-functional-correctness-validation-2504.156592025-08-26 https://scifaro.com/en/abs/bbal-a-bidirectional-block-floating-point-based-quantisation-accelerator-for-large-language-models-2504.157212025-04-23 https://scifaro.com/en/abs/insights-from-verification-training-a-verilog-generation-llm-with-reinforcement-learning-with-testbench-feedback-2504.158042025-04-23 https://scifaro.com/en/abs/hpu-high-bandwidth-processing-unit-for-scalable-cost-effective-llm-inference-via-gpu-co-processing-2504.161122025-12-19 https://scifaro.com/en/abs/fpga-based-neural-network-accelerators-for-space-applications-a-survey-2504.161732025-04-25 https://scifaro.com/en/abs/tellme-an-energy-efficient-ternary-llm-accelerator-for-prefilling-and-decoding-on-edge-fpgas-2504.162662025-04-28 https://scifaro.com/en/abs/cobra-algorithm-architecture-co-optimized-binary-transformer-accelerator-for-edge-inference-2504.162692025-04-28 https://scifaro.com/en/abs/transitive-array-an-efficient-gemm-accelerator-with-result-reuse-2504.163392025-04-24 https://scifaro.com/en/abs/eraser-efficient-rtl-fault-simulation-framework-with-trimmed-execution-redundancy-2504.164732025-04-24 https://scifaro.com/en/abs/memory-efficient-sketch-acceleration-for-handling-large-network-flows-on-fpgas-2504.168962025-04-28 https://scifaro.com/en/abs/flag-formal-and-llm-assisted-sva-generation-for-formal-specifications-of-on-chip-communication-protocols-2504.172262025-04-25 https://scifaro.com/en/abs/fine-grained-fusion-the-missing-piece-in-area-efficient-state-space-model-acceleration-2504.173332026-04-10 https://scifaro.com/en/abs/on-device-qwen2-5-efficient-llm-inference-with-model-compression-and-hardware-acceleration-2504.173762025-04-25 https://scifaro.com/en/abs/l3-dimm-pim-integrated-architecture-and-coordination-for-scalable-long-context-llm-inference-2504.175842025-04-25 https://scifaro.com/en/abs/periodic-online-testing-for-sparse-systolic-tensor-arrays-2504.186282025-04-29 https://scifaro.com/en/abs/nsflow-an-end-to-end-fpga-framework-with-scalable-dataflow-architecture-for-neuro-symbolic-ai-2504.193232025-04-30 https://scifaro.com/en/abs/dynamic-tsetlin-machine-accelerators-for-on-chip-training-at-the-edge-using-fpgas-2504.197972025-04-29 https://scifaro.com/en/abs/foldedhexatorus-an-inter-chiplet-interconnect-topology-for-chiplet-based-systems-using-organic-and-glass-substrates-2504.198782025-04-29 https://scifaro.com/en/abs/from-concept-to-practice-an-automated-llm-aided-uvm-machine-for-rtl-verification-2504.199592026-04-08 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https://scifaro.com/en/abs/neurosim-v1-5-improved-software-backbone-for-benchmarking-compute-in-memory-accelerators-with-device-and-circuit-level-non-idealities-2505.023142026-03-18 https://scifaro.com/en/abs/hardware-vs-software-implementation-of-warp-level-features-in-vortex-risc-v-gpu-2505.031022025-05-07 https://scifaro.com/en/abs/qimeng-cpu-v2-automated-superscalar-processor-design-by-learning-data-dependencies-2505.031952025-05-07 https://scifaro.com/en/abs/accllm-accelerating-long-context-llm-inference-via-algorithm-hardware-co-design-2505.037452025-05-08 https://scifaro.com/en/abs/apsq-additive-partial-sum-quantization-with-algorithm-hardware-co-design-2505.037482025-05-08 https://scifaro.com/en/abs/ai-powered-agile-analog-circuit-design-and-optimization-2505.037502025-05-09 https://scifaro.com/en/abs/improving-the-serving-performance-of-multi-lora-large-language-models-via-efficient-lora-and-kv-cache-management-2505.037562025-05-08 https://scifaro.com/en/abs/cva6s-a-superscalar-risc-v-core-with-high-throughput-memory-architecture-2505.037622025-05-09 https://scifaro.com/en/abs/splitwiser-efficient-lm-inference-with-constrained-resources-2505.037632025-05-08 https://scifaro.com/en/abs/onedse-a-unified-microprocessor-metric-prediction-and-design-space-exploration-framework-2505.037712025-10-07 https://scifaro.com/en/abs/gpu-performance-portability-needs-autotuning-2505.037802025-07-18 https://scifaro.com/en/abs/exploration-of-cryptocurrency-mining-specific-gpus-in-ai-applications-a-case-study-of-cmp-170hx-2505.037822025-05-09 https://scifaro.com/en/abs/in-situ-hardware-error-detection-using-specification-derived-petri-net-models-and-behavior-derived-state-sequences-2505.041082025-05-09 https://scifaro.com/en/abs/accelerating-triangle-counting-with-real-processing-in-memory-systems-2505.042692026-03-23 https://scifaro.com/en/abs/flexing-risc-v-instruction-subset-processors-to-extreme-edge-2505.045672025-10-29 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https://scifaro.com/en/abs/modeling-pfas-in-semiconductor-manufacturing-to-quantify-trade-offs-in-energy-efficiency-and-environmental-impact-of-computing-systems-2505.067272025-05-13 https://scifaro.com/en/abs/regular-mixed-radix-dft-matrix-factorization-for-in-place-fft-accelerators-2505.067282025-05-13 https://scifaro.com/en/abs/image-processing-application-development-on-software-configurable-processor-array-2505.068472025-05-13 https://scifaro.com/en/abs/fast-and-low-energy-approximate-full-adder-based-on-felix-logic-2505.068882026-02-26 https://scifaro.com/en/abs/ecco-improving-memory-bandwidth-and-capacity-for-llms-via-entropy-aware-cache-compression-2505.069012025-05-13 https://scifaro.com/en/abs/efficient-implementation-of-risc-v-vector-permutation-instructions-2505.071122025-06-02 https://scifaro.com/en/abs/spec2assertion-automatic-pre-rtl-assertion-generation-using-large-language-models-with-progressive-regularization-2505.079952025-05-16 https://scifaro.com/en/abs/nmp-pak-near-memory-processing-acceleration-of-scalable-de-novo-genome-assembly-2505.080712025-05-14 https://scifaro.com/en/abs/spnerf-memory-efficient-sparse-volumetric-neural-rendering-accelerator-for-edge-devices-2505.081912025-05-14 https://scifaro.com/en/abs/e-gpu-an-open-source-and-configurable-risc-v-graphic-processing-unit-for-tinyai-applications-2505.084212026-03-17 https://scifaro.com/en/abs/area-comparison-of-cheriot-and-pmp-in-ibex-2505.085412025-05-14 https://scifaro.com/en/abs/minimalist-switched-capacitor-circuits-for-efficient-in-memory-computation-of-gated-recurrent-units-2505.085992025-05-14 https://scifaro.com/en/abs/itera-llm-boosting-sub-8-bit-large-language-model-inference-via-iterative-tensor-decomposition-2505.089812025-05-15 https://scifaro.com/en/abs/dataflow-tiling-strategies-in-edge-ai-fpga-accelerators-a-comprehensive-literature-review-2505.089922025-06-03 https://scifaro.com/en/abs/automated-sar-adc-sizing-using-analytical-equations-2505.091722025-05-15 https://scifaro.com/en/abs/sega-dcim-design-space-exploration-guided-automatic-digital-cim-compiler-with-multiple-precision-support-2505.094512025-05-15 https://scifaro.com/en/abs/customizing-a-large-language-model-for-vhdl-design-of-high-performance-microprocessors-2505.096102025-05-20 https://scifaro.com/en/abs/basilisk-a-34-mm2-end-to-end-open-source-64-bit-linux-capable-risc-v-soc-in-130nm-bicmos-2505.100602025-05-16 https://scifaro.com/en/abs/an-integrated-uvm-tlm-co-simulation-framework-for-risc-v-functional-verification-and-performance-evaluation-2505.101452025-05-16 https://scifaro.com/en/abs/autorac-automated-processing-in-memory-accelerator-design-for-recommender-systems-2505.107482025-05-19 https://scifaro.com/en/abs/edgemm-multi-core-cpu-with-heterogeneous-ai-extension-and-activation-aware-weight-pruning-for-multimodal-llms-at-edge-2505.107822025-05-19 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